Getting Smarter About Tool Maintenance


Chipmakers have begun to shift to predictive maintenance for process tools, but the hefty investment in analytics and engineering efforts means it will take some time for smart maintenance to become a widespread practice. Semiconductor manufacturers need to maintain a diverse set of equipment to process the flow of wafers, dies, packaged parts, and boards running through factories. OSAT and ... » read more

Big Shifts At Very Small Geometries


The number of changes across the semiconductor industry are accelerating and widening. There are more innovations, in more places, and in more applications. What follows is a small peek at just how many significant changes are afoot, where they are happening, and who's getting recognized for their efforts. Quantum computing, but hold the math The modern electronics industry rests on multip... » read more

New Challenges Emerge With High-NA EUV


High numerical aperture EUV exposure systems are coming — as soon as 2025 by some estimates. Though certainly a less profound change than the introduction of extreme ultraviolet lithography, high-NA lithography still brings a new set of challenges for photoresists and related materials. With a higher numerical aperture, photons strike the wafer at a shallower angle. That requires thinner p... » read more

Revising 5G RF Calibration Procedures For RF IC Production Testing


Modern radio frequency (RF) components introduce many challenges to outsourced semiconductor assembly and test (OSAT) suppliers whose objective is to ensure products are assembled and tested to meet the product test specifications. The growing advancement and demand for RF products for cellphones, navigational instruments, global positioning systems, Wi-Fi, receiver/transmitter (Rx/Tx) componen... » read more

Panel Tackles Chiplet Packaging Challenges


QP Technologies recently exhibited at the first Chiplet Summit, held January 24-26 in San Jose, California. Dick Otte, CEO of our parent company Promex Industries, participated on a panel titled “Best Packaging for Chiplets Today.” Moderated by Nobuki Islam with JCET Group, the packaging panel also included Daniel Lambalot, Alphawave Semi; Laura Mirkarimi, Adeia; Syrus Ziai, Eliyan; and Mik... » read more

A Comparative Evaluation Of DRAM Bit-Line Spacer Integration Schemes


With decreasing dynamic random-access memory (DRAM) cell sizes, DRAM process development has become increasingly difficult. Bit-line (BL) sensing margins and refresh times have become problematic as cell sizes have decreased, due to an increase in BL parasitic capacitance (Cb). The main factor impacting Cb is the parasitic capacitance between the BL and the node contact (CBL-NC) [1]. To reduce ... » read more

Evolution Of The EUV Ecosystem Reflected At 2023 Advanced Lithography + Patterning


As anticipated, this year’s Advanced Lithography + Patterning Symposium was a very informative event, with many interesting papers being presented across a wide range of subjects. Many papers addressed topics relevant to leading-edge lithography, which these days means EUV lithography. With EUV lithography firmly established in high volume manufacturing (HVM), we could see in the presentation... » read more

Unleashing the Potential of Compound Semiconductors: Industry Leaders Collaborate at SEMICON Taiwan 2022 to Create Ecosystem


Delivering high-speed processing over 100 times faster than silicon, compound semiconductors have made the devices a magnet for developers of leading-edge technologies out to maximize performance in key segments including automotive, data centers and communications. With the rising profile of compound semiconductors as the backdrop, leading experts gathered at the Power and Opto Semiconductor F... » read more

FPGA-based Infrastructure, With RISC-V Prototype, to Enable Implementation & Evaluation of Cross-Layer Techniques in Real HW (Best Paper Award)


A technical paper titled "MetaSys: A Practical Open-Source Metadata Management System to Implement and Evaluate Cross-Layer Optimizations" was published by researchers at University of Toronto, ETH Zurich, and Carnegie Mellon University. This paper won the Best Paper Award at the HiPEAC 2023 conference. Abstract: "This paper introduces the first open-source FPGA-based infrastructure, MetaSy... » read more

Learning The AMS Circuit Representation From Layout Positions (UT Austin/ NVIDIA)


A recent technical paper titled "TAG: Learning Circuit Spatial Embedding From Layouts" was published by researchers at UT Austin and NVIDIA. Abstract "Analog and mixed-signal (AMS) circuit designs still rely on human design expertise. Machine learning has been assisting circuit design automation by replacing human experience with artificial intelligence. This paper presents TAG, a new parad... » read more

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