Panel Tackles Chiplet Packaging Challenges

A logic and functional specification for chiplets is needed to enable adoption by smaller companies.


QP Technologies recently exhibited at the first Chiplet Summit, held January 24-26 in San Jose, California. Dick Otte, CEO of our parent company Promex Industries, participated on a panel titled “Best Packaging for Chiplets Today.” Moderated by Nobuki Islam with JCET Group, the packaging panel also included Daniel Lambalot, Alphawave Semi; Laura Mirkarimi, Adeia; Syrus Ziai, Eliyan; and Mike Kelly, Amkor Technology. Below are some highlights and comments that emerged from the discussion.

Chiplet packaging panel participants (L to R): Daniel Lambalot, Dick Otte, Syrus Ziai, Laura Mirkarimi, Mike Kelly and moderator Nobuki Islam. (Photo courtesy of Rosie Medina, QP Technologies VP of sales & marketing.)

1. Does the chiplet packaging solution violate Moore’s Law?

Moore himself had allowed for the fact that it might prove to be more economical to build large systems out of smaller functions, which are separately packaged and interconnected. While the packaging of chiplets is definitely moving into the third dimension, this aspect of chip manufacturing is covered under Moore’s Law. The chiplet is essentially a continuation of the trend toward greater functionality per unit volume that has taken place over time. Moore established a vision for the industry, and chiplets are the next evolutionary step. Because leading-edge device dimensions are now down to a few atoms, we need to go to 3D.

2. What are the key challenges for chiplet packaging?

There are multiple challenges to chiplet and 3D packaging. Multi-chiplet design tools, thermal management, interposer choices, interconnects methods such as through-silicon vias (TSVs), flip-chip, hybrid bonding, bumping, and testing, especially of individual chiplets and at intermediate assembly stages. Standards will help alleviate some of the challenges, but it will come down to meeting the customer requirements in an economical manner.

3. Is IP an issue for the chiplet package when we deal with designs from various sources to integrate the chiplet?

The design challenge for AMD and Intel is different than for smaller companies. Elements of design and integration are easier, as they design and build most of the parts in the package. Smaller companies, on the other hand, need to buy off-the-shelf parts and design the interposers and packages, so there will need to be a logic and functional specification for the chiplets. A unified platform might be helpful, but the industry needs to work through the standards to develop that platform. A de facto standard might arise due to designers adopting immediately available chiplets and the required immediate manufacturing need.

4. The business model for chiplets is highly dependent upon market size; we may need an ecosystem and infrastructure investment to support a robust service for chiplets. Will the market be big enough to justify the investment?

From the amount of activity surrounding 3D packaging, the larger companies are already investing at a significant rate. Growing new capacity without revolutionizing the manufacturing lines will be an important aspect of growing the business profitably. There will need to be a long continuum of adoption as the industry shifts to finer lines and smaller pitches that will enable the industry to invest so the segment can grow quickly, but also expand for the long haul. Some technologies, such as embedded bridges, may be more challenging for broad industry implementation.

5. Hybrid bonding is being used by some of the key fabs for wafer-to-wafer bonding. Do you think this will be adopted by OSATs? 

The consensus is that OSAT will adopt hybrid bonding, as it is one of the ways to keep shrinking the package and reducing parasitics.

6. What’s next after hybrid bonding?

Hybrid bonding will be with the chiplet space for a long time.

7. What areas should we focus on for a shorter time-to-market for chiplet packaging?

The industry needs to get good control over all the parts needed to put the system together. To get to a shorter time to market, better design tools are needed that allow you to figure out how to glue them together so that you know how to partition the chips, and how to do interconnect for both chip first and chip last approaches. Also, reducing the time and cost to deliver new interposers is important.

8. Are the existing design/simulation tools capable enough to meet chiplet design requirements? 

It appears that the majority of the tools needed are in place to make this happen, but the designers need to catch up.

9. What area do you think software design companies need to focus on to improve their chiplet capabilities? 

The software companies need to develop a higher level tool that will support integrating multiple die/chiplets and enable the design of the interposer or interconnect structure. A move to silicon and maybe glass from organic dielectric interposers may be necessary to improve reliability, provide the interconnect density for interposers.

10. What other improvements need to be made to our supply chain ecosystem to support future demand? 

Do what is practical for today. Develop test vehicles and get manufacturing going. If common interfaces can be developed that everyone can qualify to, which includes not having to redesign legacy chips, then the industry can start moving forward in a meaningful way.


chip99monk says:

Just like assembling many Packaged Dies on PCBs, Integrating Chiplets densely by Adv. Packaging too is going to have some penalties re: performance and costs over SoCs, but can still be attractive for well-known reasons (design reuse, Fab utilization, yield). Adv. Packaging technologies were developed mostly at US based IDMs, which the Fabless community (w/ their “OUT of sight, OUT of mind” attitude towards the PHYSICS intensive Hardware Mfr. technologies) have enjoyed through their offshore Foundries and OSATs, who picked them up FREE via open technical conferences and smaller US Co.s peddling them. So the Fabless seem to have taken for granted the hardware technology development needs for Chiplet integration, instead keep going on and on about the challenges in Design of Chiplets and re integrating them at the Package level that are comparatively TRIVIAL. All available Adv. Packaging technologies (invented, even transferred to High Volume Mfr. right here in the US) are already in use by the Foundries & OSATs, but for Chiplet re: integration, especially in 3D stacks, new hardware manufacturing technologies need to be developed. So if the fabless community and their VENTURE CAPITALISTS do not want to wait forever for their Foundries and OSATs to develop new technologies, then they had better invest in R&D within the US — the source of nearly 90% of all Adv. Packaging technologies in use today — from solder bumped and u Pillar Flip Chip, Organic and Silicon substrates all the way to the latest and greatest — Hybrid Copper Bond.

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