MIMO Application Framework


Massive MIMO is an exciting area of 5G wireless research. For next-generation wireless data networks, it promises significant gains that offer the ability to accommodate more users at higher data rates with better reliability while consuming less power. Using the NI Massive MIMO Software Architecture, researchers can build Massive MIMO testbeds to rapidly prototype large-scale antenna systems u... » read more

Application-Specific Power Performance Optimizer Based On Chip Telemetry


As datacenter power consumption continues to pose cooling and cost challenges, and battery driven devices are expected to last longer between charges, the search for advanced power management mechanisms continues. A modern design must balance between maximizing performance, consuming the least amount of power, and guaranteeing no failures in field. The latter requires safety margins which tr... » read more

An All-Optical General-Purpose CPU And Optical Computer Architecture (Akhetonics)


A technical paper titled “An All-Optical General-Purpose CPU and Optical Computer Architecture” was published by researchers at Akhetonics. Abstract: "Energy efficiency of electronic digital processors is primarily limited by the energy consumption of electronic communication and interconnects. The industry is almost unanimously pushing towards replacing both long-haul, as well as local c... » read more

Safeguarding IoT Devices With SESIP And PSA Certified Root Of Trust IP


IoT is everywhere. By the end of 2024, it’s forecasted that there will be a staggering 207 billion IoT devices in the world, that’s 25 each for every human being on Earth. The connectivity of IoT devices brings great value for consumers and businesses alike, but with great connectivity comes greater vulnerability to a wide variety of malicious attacks from cyber criminals. IoT devices ar... » read more

Chip Industry Technical Paper Roundup: Mar. 11


New technical papers added to Semiconductor Engineering’s library this week. [table id=205 /] More ReadingTechnical Paper Library home » read more

Research Bits: Mar. 11


Ferroelectric nanosheets Engineers from the University of Sydney, RMIT University, University of New South Wales, and University of Technology Sydney created a liquid metal alloy of tin, zirconium, and hafnium. The alloy has a thin oxide layer crust that enables it to be used to harvest ultra-thin tin oxide nanosheets doped with hafnium zirconium oxide, which could then be 2D printed on a subs... » read more

Accelerate Complex Algorithms With Adaptable Signal Processing Solutions


Technology is continuously advancing and exponentially increasing the amount of data produced. Data comes from a multitude of sources and formats, requiring systems to process different algorithms. Each of these algorithms present their own challenges including low-latency and deterministic processing to keep up with incoming data rates and rapid response time. Considering that many of these se... » read more

Chip Industry Week In Review


By Adam Kovac, Gregory Haley, and Liz Allan. Cadence plans to acquire BETA CAE Systems for $1.24 billion, the latest volley in a race to sell multi-physics simulation and analysis across a broad set of customers with deep pockets. Cadence said the deal opens the door to structural analysis for the automotive, aerospace, industrial, and health care sectors. Under the terms of the agreement, 6... » read more

Ultrathin vdW Ferromagnet at Room Temperature (MIT)


A technical paper titled “Current-induced switching of a van der Waals ferromagnet at room temperature” was published by researchers at Massachusetts Institute of Technology (MIT). Abstract: "Recent discovery of emergent magnetism in van der Waals magnetic materials (vdWMM) has broadened the material space for developing spintronic devices for energy-efficient computation. While there has... » read more

K-Fault Resistant Partitioning To Assess Redundancy-Based HW Countermeasures To Fault Injections


A technical paper titled “Fault-Resistant Partitioning of Secure CPUs for System Co-Verification against Faults” was published by researchers at Université Paris-Saclay, Graz University of Technology, lowRISC, University Grenoble Alpes, Thales, and Sorbonne University. Abstract: "To assess the robustness of CPU-based systems against fault injection attacks, it is necessary to analyze the... » read more

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