From DIY To Advanced NoC Solutions: The Future Of MCU Design
By Andy Nightingale - 30 Jan, 2025 - Comments: 0

The evolution of microcontrollers (MCUs) has significantly transformed embedded systems, shifting from simple, standalone processors to complex, multifunctional units that rival traditional systems-on-chip (SoCs). These advancements are fueled by the demand for increased computational efficiency, cutting-edge features like AI and machine learning (ML) integration, and the need to address growin... » read more

Chip Architectures Becoming Much More Complex With Chiplets
By Ed Sperling and Ann Mutschler - 30 Jan, 2025 - Comments: 0

The migration from monolithic SoCs to chiplet-based designs is creating a confusing array of options and tradeoffs for design teams working at the leading edge, and the number of choices is only going to increase as third-party chiplets begin pouring into the market. That hasn't dampened the appetite for chiplets, however, which are deemed essential for future generations of semiconductors f... » read more

Gold In The Machine: Scaling Infrastructure For The Age Of AI
By Jenn Mullen - 30 Jan, 2025 - Comments: 0

During the gold rush, hopeful prospectors flooded the west to make their fortunes in gold. Today, technology pioneers are looking to stake their claim in the realm of artificial intelligence (AI). Price Waterhouse Cooper (PWC) estimates that 45% of total global economic gains by 2030 will be driven by AI as more sectors embrace the productivity and product enhancement benefits of AI. PWC’s ... » read more

AI Infrastructure At A Crossroads
By Ramin Farjadrad - 30 Jan, 2025 - Comments: 0

By Ramin Farjadrad and Syrus Ziai There is a big push to achieve greater scale, performance and sustainability to fuel the AI revolution. More speed, more memory bandwidth, less power — these are the holy grails. Naturally, the one-two punch of StarGate and DeepSeek last week has raised many questions in our ecosystem and with our various stakeholders. Can DeepSeek be real? And if so, w... » read more

Accelerate IC Design With Shift-Left DRC
By John Ferguson - 30 Jan, 2025 - Comments: 0

By John Ferguson and Lei Ling The increasing complexity of integrated circuit (IC) designs is straining our traditional design rule checking (DRC) methods. The iterative "construct by correction" approach that worked well for simpler, custom layouts is now creating substantial runtime and resource bottlenecks, hindering design teams' ability to efficiently verify their advanced designs and m... » read more

Microsoft Accelerates DRC With Shift-Left Verification
By Siemens EDA - 30 Jan, 2025 - Comments: 0

As integrated circuit (IC) designs grow in complexity, traditional design rule checking (DRC) methods struggle to keep pace. Originally developed for simpler, custom layouts, traditional DRC uses an iterative “construct by correction” method. However, with the rise of automation and multi-layered design hierarchies, relying on traditional sequential DRC approaches can create substantial run... » read more

Chiplets Still A Challenge With UCIe 2.0
By Brian Bailey - 30 Jan, 2025 - Comments: 0

Plug-and-play chiplets are a popular goal, but does UCIe 2.0 move us any closer to that becoming a reality? The problem is that the current drivers of the standard are not after interoperability in the way that plug-and-play requires. Released in August 2024, UCIe 2.0 touts higher bandwidth density and improved power efficiency, as well as new features supporting 3D packaging, a manageable s... » read more

Design Customization Puts Heavy Burden On Verification
By Ann Mutschler - 30 Jan, 2025 - Comments: 0

Experts At The Table: The pressure on verification engineers to ensure a device will function correctly has increased exponentially as chips become more complex and heterogeneous. Semiconductor Engineering sat down with a panel of experts, including Josh Rensch, director of application engineering at Arteris; Matt Graham, senior group director for verification software product management at Cad... » read more

Fast Monte Carlo Simulations For Timing Variation Analysis
By Vinod Khera - 30 Jan, 2025 - Comments: 0

Process variations and device mismatches profoundly affect the latest ultra-small geometrical processes. Complexity creates additional factors that impact device manufacturing variability, which in turn impact overall yield. Monte Carlo (MC) simulations use repeated random sampling to relate process variations to circuit performance and functionality, thus determining how they impact yield. How... » read more

Apple CPU Attacks: SLAP and FLOP (Georgia Tech, Ruhr University Bochum)
By Technical Paper Link - 29 Jan, 2025 - Comments: 0

Two technical papers were published by researchers at Georgia Tech and Ruhr University Bochum detailing CPU side-channel attack vulnerabilities on Apple devices that could reveal confidential data. FLOP: Breaking the Apple M3 CPU via False Load Output Predictions"  Authors: Jason Kim, Jalen Chuang, Daniel Genkin and Yuval Yarom 2025. "We present FLOP, another speculative execution att... » read more

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