Hyperconvergence Of Design For Test And Physical Design


By Sri Ganta and Hyoung-Kook Kim In today’s highly competitive semiconductor industry, chip-design companies strive for competitive advantages by optimizing designs for PPA (Power, Performance, Area). Along with the functional logic, design cores also comprise DFT (Design for Test) logic that spreads across the design. The DFT logic also must be optimized for PPA, requiring design implemen... » read more

Silent Data Errors Still Slipping Through The Cracks


Silent data corruption errors in large server farms have become a major concern of cloud users, hyperscalers, processor manufacturers and the test community. Silent data errors (also called silent data corruption errors) are hardware errors that occur when an incorrect computational result from a processor core goes undetected by the system. The data is silently corrupted because neither sof... » read more

Simulation Closes Gap Between Chip Design Optimization And Manufacturability


Simulation is playing an increasingly critical and central role throughout the design-through-manufacturing flow, fusing together everything from design to manufacturing and test in order to reduce the number and cost of silicon respins. The sheer density of modern chips, combined with advanced packaging techniques like 3D stacking and heterogeneous integration, has made iterative physical p... » read more

IC Equipment Communication Standards Struggle As Data Volumes Grow


The tsunami of data produced during wafer fabrication cannot be effectively leveraged without standards. They determine how data is accessed from equipment, which users need data access and when, and how fast it can be delivered. On top of that, best practices in data governance and data quality are needed to effectively interpret collected data and transfer results. When fab automation and ... » read more

Early Detection Of C-RES Degradation On High-Current Power Planes


Probe-card or device contactor damage can be dramatic and catastrophic, with yield dropping drastically very quickly. What is not dramatic is the hypothesized slow probe needle or contactor degradation process that might precede catastrophic failure. Such degradation is difficult to detect in the early stages, when probe cards, die, and packages continue to yield normally. A key goal is to dete... » read more

Chip Industry Technical Paper Roundup: Feb. 10


New technical papers recently added to Semiconductor Engineering’s library: [table id=405 /] Find all technical papers here. Also find more research and latest news here. » read more

Research Bits: Feb. 10


Speeding up 3D NAND etch Researchers from Lam Research, the University of Colorado Boulder, and Princeton Plasma Physics Laboratory (PPPL) investigated ways to speed up the cryogenic reactive ion etching process for 3D NAND by using a combined hydrogen fluoride gas to create the plasma. “Cryo etch with the hydrogen fluoride plasma showed a significant increase in the etching rate compared... » read more

Introduction To Voltage Droop And Mitigation


Voltage droop continues to plague high-performance SoCs, and not all mitigation systems are designed equal. When you have a choice, its always better to measure and quantify the differences. This paper provides a system-level introduction to voltage droop, along with a framework for measuring potential Vmin savings, and a way to answer the age-old question, "Is my mitigation system fast enough?... » read more

Wafer-Scale Computing for LLMs (U. of Edinburgh, Microsoft)


A new technical paper titled "WaferLLM: A Wafer-Scale LLM Inference System" was published by researchers at University of Edinburgh and Microsoft Research. Abstract "Emerging AI accelerators increasingly adopt wafer-scale manufacturing technologies, integrating hundreds of thousands of AI cores in a mesh-based architecture with large distributed on-chip memory (tens of GB in total) and ultr... » read more

Potential of Wireless Interconnects For Improving Performance And Flexibility Of Multi-Chip AI Accelerators


A new technical paper titled "Exploring the Potential of Wireless-enabled Multi-Chip AI Accelerators" was published by researchers at Universitat Politecnica de Catalunya. Abstract "The insatiable appetite of Artificial Intelligence (AI) workloads for computing power is pushing the industry to develop faster and more efficient accelerators. The rigidity of custom hardware, however, conflict... » read more

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