MFMIS FeTFETs For Energy-Efficient, Scalable CIM Hardware Accelerators (Seoul National University)
By Technical Paper Link - 26 Jan, 2026 - Comments: 0

A new technical titled "Impact of Random Phase Distribution on Ferroelectric Tunnel Field-Effect Transistors With Mitigation Strategies for Compute-in-Memory Applications" was published by researchers at Seoul National University. Abstract "This work presents, for the first time, an investigation of the impact of random phase distribution on ferroelectric (FE) tunnel field-effect transist... » read more

Software-Defined Systems
By Ed Sperling - 26 Jan, 2026 - Comments: 0

Using high-level software languages to define semiconductors is faster, easier, and allows for more changes long before the RTL stage. This is especially useful for chiplets and embedded accelerators, which are narrower in scope and more targeted at different workloads and specific domains. But there are some caveats for engineers working in this space. Russell Klein, program director for Sieme... » read more

Balancing Training, Quantization, And Hardware Integration In NPUs
By Ann Mutschler - 26 Jan, 2026 - Comments: 0

Experts At The Table: AI/ML is driving a steep ramp in neural processing unit (NPU) design activity for everything from data centers to edge devices such as PCs and smartphones. Semiconductor Engineering sat down to discuss this with Jason Lawley, director of product marketing, AI IP at Cadence; Sharad Chole, chief scientist and co-founder at Expedera; Steve Roddy, chief marketing officer at Qu... » read more

Hypergraph-based Techniques To Map Spiking Neural Networks on Neuromorphic HW (Politecnico di Milano)
By Technical Paper Link - 25 Jan, 2026 - Comments: 0

A new technical paper titled "A Case for Hypergraphs to Model and Map SNNs on Neuromorphic Hardware" was published by researchers at Politecnico di Milano. Abstract "Executing Spiking Neural Networks (SNNs) on neuromorphic hardware poses the problem of mapping neurons to cores. SNNs operate by propagating spikes between neurons that form a graph through synapses. Neuromorphic hardware mimic... » read more

Overview of ALD-Driven Oxide Semiconductors for High Density, Low Power Memory Architectures (Hanyang Univ., imec)
By Technical Paper Link - 25 Jan, 2026 - Comments: 0

A new technical paper titled "Oxide Semiconductor for Advanced Memory Architectures: Atomic Layer Deposition, Key Requirement and Challenges" was published by researchers a Hanyang University and imec. Abstract "Oxide semiconductors (OSs), introduced by the Hosono group in the early 2000s, have evolved from display backplane materials to promising candidates for advanced memory and logic ... » read more

Better Contact Resistance in Top-Gate CNFETs through Self-Aligned MoOx Nanoparticle Contact Doping (NYCU et al.)
By Technical Paper Link - 24 Jan, 2026 - Comments: 0

A new technical paper titled "Improving Contact Resistance in Top-Gate Carbon Nanotube Transistor through Self-Aligned MoOx Nanoparticle Contact Doping" was published by researchers at National Yang Ming Chiao Tung University and National Center for Instrumentation Research. "Carbon nanotubes (CNTs) are promising candidates for next-generation back-end-of-line (BEOL) compatible devices due t... » read more

Overview and Comparison of Devices Used For Optical Waveguide-to-Waveguide Coupling (MIT et al.)
By Technical Paper Link - 24 Jan, 2026 - Comments: 0

A new technical paper titled "Advances in waveguide to waveguide couplers for 3D integrated photonic packaging" was published by researchers at MIT and Bridgewater State University. Abstract "In this paper, we provide an overview and comparison of devices used for optical waveguide-to-waveguide coupling including inter-chip edge couplers, grating couplers, free form couplers, evanescent cou... » read more

Outlier-aware Quantization Framework Co-designed With Heterogeneous NVM For SLM Deployment on Edge Platforms (UCSD et al.)
By Technical Paper Link - 24 Jan, 2026 - Comments: 0

  A new technical paper titled "QMC: Efficient SLM Edge Inference via Outlier-Aware Quantization and Emergent Memories Co-Design" was published by researchers at University of California San Diego and San Diego State University. Abstract "Deploying Small Language Models (SLMs) on edge platforms is critical for real-time, privacy-sensitive generative AI, yet constrained by memory, ... » read more

Confidentiality-preserving Framework For Secure On-Chip Communication in NoC Architectures
By Technical Paper Link - 24 Jan, 2026 - Comments: 0

A new technical paper, "Secure Multi-Path Routing with All-or-Nothing Transform for Network-on-Chip Architectures," was published by researchers at University of Florida. Abstract "Ensuring Network-on-Chip (NoC) security is crucial to design trustworthy NoC-based System-on-Chip (SoC) architectures. While there are various threats that exploit on-chip communication vulnerabilities, eavesdrop... » read more

A Verification Framework For Trojan Detection (U. of Kansas, U. of Florida)
By Technical Paper Link - 23 Jan, 2026 - Comments: 0

A new technical paper "COVERT: Trojan Detection in COTS Hardware via Statistical Activation of Microarchitectural Events" was published by researchers at University of Kansas and University of Florida. Abstract "Commercial Off-The-Shelf (COTS) hardware, such as microprocessors, are widely adopted in system design due to their ability to reduce development time and cost compared to custom ... » read more

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