Agentic AI In Chip Manufacturing

By Ed Sperling - 28 Jan, 2026 - Comments: 1

Agentic AI — breaking AI into individual agents that can work together and collaboratively — will be the real game changer for AI in chip manufacturing. By taking humans out of the loop, these agents can be programmed using natural language to automatically solve problems and improve efficiency. Jon Herlocker, vice president and general manager of software analytics at Cohu, talks about w... » read more

The Next-Generation of Circuit Simulation in RF EDA

By Keysight - 28 Jan, 2026 - Comments: 0

Radio-Frequency (RF) Electronic Design Automation (EDA) is at a turning point. Historically, engineers adapted their workflows to rigid software tools, often sacrificing flexibility and efficiency. With the rise of increasingly complex, multi-domain hardware systems, these constraints are no longer sustainable. Keysight is reimagining RF simulation as a programmatically controlled, extensible p... » read more

Blog Review: Jan. 28

By Jesse Allen - 28 Jan, 2026 - Comments: 0

Synopsys' Dana Neustadter and Vincent van der Leest argue that a hardware-based approach to security is required to fully address the risks introduced by modern AI architectures and the distributed workloads they support. Siemens EDA's Tova Levy examines multiphysics challenges in 3D-IC designs and outlines three design imperatives to identify risks earlier and support PPA, reliability, and ... » read more

New Innovative Way to Functionally Verify Heterogeneous 2D/3D Package Connectivity

By Siemens EDA - 28 Jan, 2026 - Comments: 0

The heterogeneous integration of multiple chiplets in a single packaging platform is critical for many high performance compute segemnts such as AI, Hyperscalers, Cloud datacenters, Neural processors and even autonomous vehicles. With the quantity of chiplets commonly exceeding double-digit numbers. Add to that the increasing usage of high-speed, low power and low latency high-bandwidth-memory ... » read more

Will It Blend: A Methodology for Verifying the Hardware/Software Interface in Complex SoCs

By Arteris - 28 Jan, 2026 - Comments: 0

Verification of modern System on Chip (SoC) designs involve many components. Hardware Description Languages (VHDL, System Verilog), Unified Power Format (UPF), Software Languages (C#/C++), Interconnect standards (IP-XACT, AMBA), and specialty purpose-built layers such as the Universal Verification Methodology (UVM) and System Verilog Assertions (SVA). This deck explores using Arteris SoC Integr... » read more

Automated High-Speed Interface Routing in Multi-Die Designs

By Synopsys - 28 Jan, 2026 - Comments: 0

2.5D and 3D Multi-die design is revolutionizing chip integration by enabling thousands of high-speed connections between dies (also called chiplets). Discover how close placement of dies boosts bandwidth, minimizes latency, and maximizes data throughput. Read this white paper to find out about the importance of interconnectivity planning and die-to-die signal routing for successful m... » read more

Voice is the New UI

By Cadence - 28 Jan, 2026 - Comments: 0

Recent years have seen a paradigm shift in the user interface (UI) of our computers and client devices, and this is gaining momentum. Advancements in large language models (LLM), small language models (SLM), energy-efficient systems on chip (SoC), and on-device AI processing are making voice input the new “keyboard”. Read more here. Fig.1: Voice Processing Pipeline On-De... » read more

Research Bits: Jan. 27

By Jesse Allen - 27 Jan, 2026 - Comments: 0

Analog in-memory compute Researchers from Politecnico di Milano, Peking University, and Hewlett Packard Labs developed a Closed-Loop In-Memory Computing (CL-IMC) chip to reduce data movement between memory and processor. The fully integrated analog accelerator uses two 64×64 arrays of programmable SRAM cells along with integrated components including operational amplifiers and analog-to-di... » read more

Chip Industry Technical Paper Roundup: Jan. 27

By Linda Christensen - 27 Jan, 2026 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: [table id=517 /] Find more semiconductor research papers here. » read more

Semiconductor Supply Chain Security Using Side-Channel Power Measurements and Generative Adversarial Networks (Cornell)

By Technical Paper Link - 26 Jan, 2026 - Comments: 0

A new technical paper titled "Out-of-Band Power Side-Channel Detection for Semiconductor Supply Chain Integrity at Scale" was published by researchers at Cornell University. Abstract "Out-of-band screening of microcontrollers is a major gap in semiconductor supply chain security. High-assurance techniques such as X-ray and destructive reverse engineering are accurate but slow and expensiv... » read more

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