Integration technologies to unify design and verification.
Verification of modern System on Chip (SoC) designs involve many components. Hardware Description Languages (VHDL, System Verilog), Unified Power Format (UPF), Software Languages (C#/C++), Interconnect standards (IP-XACT, AMBA), and specialty purpose-built layers such as the Universal Verification Methodology (UVM) and System Verilog Assertions (SVA). This deck explores using Arteris SoC Integration technologies to “blend” these components together by proposing a more efficient methodology to increase productivity and help ensure first-time SoC project success.
Read more here.
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