Week in Review: IoT, Auto, Security


Executive Changes Rambus' board of directors named Luc Seraphin, senior vice president and general manager of the company's Memory and Interfaces Division, as interim CEO while it searches for a replacement for Ron Black. The board terminated Black this week, saying the reason for termination did not involve Rambus' financial and business performance. The company also named Mike Noonen as se... » read more

Week In Review: Design, Low Power


M&A Siemens acquired Austemper Design Systems, which provides tools for functional safety and safety-critical designs. Founded in 2015, Texas-based Austemper adds state-of-the-art safety analysis, auto-correction and fault simulation technology to address random hardware faults, as well as correct and harden vulnerable areas, subsequently performing fault simulation to ensure the design is... » read more

The Week In Review: Design


Tools Mentor Graphics uncorked the latest version of its Catapult high-level synthesis platform, adding a formal-based C Property Checker tool to automatically identify and formally prove hard-to-find issues like uninitialized memory, divide by 0, and array bounds errors in the users' HLS C++/SystemC model. IP ARM unveiled the Cortex-A73 and Mali-G71 processors. According to ARM, the g... » read more

Bridging the IP Divide


IP reuse enabled greater efficiency in the creation of large, complex SoCs, but even after 20 years there are few tools to bridge the divide between the IP provider and the IP user. The problem is that there is an implicit fuzzy contract describing how the IP should be used, what capabilities it provides, and the extent of the verification that has been performed. IP vendors have been trying to... » read more

The Week In Review: Design


IP Cadence rolled out a portfolio of stacked die memory verification IP to support Wide I/O-2, Hybrid Memory Cube, high-bandwidth memory, and DDR4-3DS. Included are direct memory access for read, write, save, preload and comparison of memory contents, assertions, error configurability, and a built-in address manager. ARM rolled out additions to its enterprise-class SoC interconnects for qua... » read more