Reliable AI accelerators; better contact resistance; side-channel attack using memory reorderings; scaling 2D nanoribbons; waveguide to waveguide couplers for 3D photonics packaging; photonics gate array; SLM edge inference; NoC architectures; trojan detection.
New technical papers recently added to Semiconductor Engineering’s library:
| Technical Paper | Research Organizations |
|---|---|
| Improving Contact Resistance in Top-Gate Carbon Nanotube Transistor through Self-Aligned MoOx Nanoparticle Contact Doping | National Yang Ming Chiao Tung University and National Center for Instrumentation Research |
| Memory DisOrder: Memory Re-orderings as a Timerless Side-channel | University of Washington, Duke, UCSC, Raytheon and Microsoft |
| Scaling of 2D Semiconductor Nanoribbons for High-Performance Electronics | Purdue, National University of Singapore, Nexstrom, and Dankook University |
| Advances in waveguide to waveguide couplers for 3D integrated photonic packaging | MIT and Bridgewater State University |
| The Quest for Reliable AI Accelerators: Cross-Layer Evaluation and Design Optimization | Peking University and Beijing Advanced Innovation Center for ICs |
| High-Speed Non-Volatile Barium Titanate Field Programmable Photonic Gate Array | Universitat Politècnica de València, iPronics Programmable Photonic, Lumiphase, Univ. of West Attica and CEA-Leti |
| QMC: Efficient SLM Edge Inference via Outlier-Aware Quantization and Emergent Memories Co-Design | UCSD and San Diego State |
| Secure Multi-Path Routing with All-or-Nothing Transform for Network-on-Chip Architectures | University of Florida |
| COVERT: Trojan Detection in COTS Hardware via Statistical Activation of Microarchitectural Events | University of Kansas and University of Florida |
Find more semiconductor research papers here.
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