GPU Acceleration for Pixel-based Computing in Various Mask Processing and Verification Steps


A technical paper titled "Leaping into the curvy world with GPU accelerated O(p) computing" was published by researchers at D2S, Inc. The papers discusses the advantages of using GPU acceleration for pixel-based computing during various mask processing and verification steps.  It found that the O(p) approach for GPU acceleration is effective in handling data processing for curvy masks. F... » read more

Ruthenium Interconnects On Tap


Chipmakers' focus on new interconnect technology is ramping up as copper's effectiveness continues to diminish, setting the stage for a significant shift that could improve performance and reduce heat at future nodes and in advanced packages. The introduction of copper interconnects in 1997 upended the then-standard tungsten via/aluminum line metallization scheme. Dual damascene integration ... » read more

Interconnects: Criteria For Alternative Metal Benchmarking And Selection (Imec, KU Leuven)


A technical paper titled “Selecting Alternative Metals for Advanced Interconnects” was published by researchers at imec and KU Leuven. Abstract “Today, interconnect resistance and reliability are key limiters for the performance of advanced CMOS circuits. As transistor scaling is slowing, interconnect scaling has become the main driver for circuit miniaturization, and interconnect lim... » read more

Blog Review: June 19


Siemens' John McMillan and Todd Burkholder suggest using an automatic formal-based approach to verifying chiplet package connections early in the design process. Cadence's Veena Parthan explores the intricacies of wind tunnel testing in automotive design and how the collaborative relationship between computational fluid dynamics (CFD) and wind tunnels has resulted in accelerated and more nua... » read more

What’s Missing In Test


Experts at the Table: Semiconductor Engineering sat down to discuss how functional test content is brought up at first silicon, and the balance between ATE and system-level testing, with Klaus-Dieter Hilliges, V93000 platform extension manager at Advantest Europe; Robert Cavagnaro, fellow in the Design Engineering Group at Intel (responsible for manufacturing and test strategy of data center... » read more

Plasma Etching : Challenges And Options Going Forward (UMD, IBM, Lam Research, Intel, Samsung et al.)


A new technical paper titled "Future of plasma etching for microelectronics: Challenges and opportunities" was published by researchers from numerous academic institutions and companies, including University of Maryland, IBM, Arkema, UCLA, Lam Research, Intel Corporation, Samsung, Air Liquide, Sony, and many others. Abstract: "Plasma etching is an essential semiconductor manufacturing techn... » read more

Research Bits: June 18


Gallium nitride can take the heat Researchers from Massachusetts Institute of Technology (MIT), the UAE's Technology Innovation Institute, Ohio State University, Rice University, and Bangladesh University of Engineering and Technology investigated the performance of ohmic contacts in a gallium nitride (GaN) device at extremely high temperatures, such as those that would be required for devices... » read more

Chip Industry Technical Paper Roundup: June 18


New technical papers added to Semiconductor Engineering’s library this week. [table id=234 /] More ReadingTechnical Paper Library home » read more

IC Industry’s Growing Role In Sustainability


The massive power needs of AI systems are putting a spotlight on sustainability in the semiconductor ecosystem. The chip industry needs to be able to produce more efficient and lower-power semiconductors. But demands for increased processing speed are rising with the widespread use of large language models and the overall increase in the amount of data that needs to be processed. Gartner estima... » read more

Chip Industry Week In Review


Samsung unveiled its latest 2nm and 4nm process nodes, plus its AI solutions during the Samsung Foundry Forum. The company also introduced an aggressive roadmap for the next few years that includes 3D-ICs with logic-on-logic, starting in 2025; custom HBM with built-in logic; backside power delivery on 2nm technology in 2027; and co-packaged optics. In presentations at the event, the company als... » read more

← Older posts Newer posts →