Chiplets Make Progress Using Interconnects As Glue


Breaking up SoCs into their component parts and putting those and other pieces together in some type of heterogeneous assembly is beginning to take shape, fueled by advances in interconnects, complex partitioning, and industry learnings about what works and what doesn't. While the vision of plug-and-play remains intact, getting there is a lot more complicated than initially imagined. It can ... » read more

Revolutionizing High-Performance Silicon With Next-Gen Chiplets


By Shivi Arora and Sue Hung Fung As 5G wireless communications systems continue to be deployed, enterprises are busy planning for 6G—the next generation of wireless communications set to transform our lives. Poised to merge communication and computing, 6G promises to create a hyperconnected world that blends digital and physical experiences with ultra-fast speeds and low latency as a start... » read more

HW and SW Architecture Approaches For Running AI Models


How best to run AI inference models is a current topic of much debate as a wide breadth of systems companies look to add AI to a variety of systems, spurring both hardware innovation and the need to revamp models. Hardware developers are making progress with AI accelerators and SoCs. But on the model side, questions abound about whether the answer might come from revisiting older, less compl... » read more

Locking When Emulating Xtensa LX Multi-Core On A Xilinx FPGA


Today's high-performance computing systems often require the designer to instantiate multiple CPU or DSP cores in their subsystem. However, the performance gained by using multiple CPUs comes with additional programming complexity, especially when accessing shared memory data structures and hardware peripherals. CPU cores need to access shared data in an atomic fashion in a multi-core environme... » read more

RISC-V Conformance


Experts At The Table: Despite growing excitement and participation in the development of the RISC-V ecosystem, significant holes remain in the development flow. One of the most concerning is conformance, which must exist before software portability becomes possible. Semiconductor Engineering discussed the issue with John Min, vice president of customer service at Arteris; Zdeněk Přikryl, CTO... » read more

Mastering Cyber Awareness: Training For The Digital Battlefield


In today’s digital battlefield, cyber awareness is crucial for warfighters. To effectively prepare them, it’s essential to create realistic and detailed models of mobile networks, encompassing both physical and virtual infrastructure. This is where network modeling software comes into play, offering a high-fidelity approach to enhance cyber situational awareness. A high-fidelity modeling an... » read more

Accelerate AI SoC Designs with NoC Tiling


Network-on-chip (NoC) tiling technology is revolutionizing AI and machine learning-enabled semiconductor designs. This emerging approach uses proven, robust network-on-chipIP to facilitate scaling, condense design time, speed testing and reduce design risk. It allowsSoC architects to create modular, scalable designs by replicating soft tiles across the chip. Each soft tile represents a self-con... » read more

Blog Review: Oct. 30


Synopsys' Frank Schirrmeister argues that hardware-assisted verification techniques like emulation and prototyping are essential to help engineers improve design behavior to manage complexity and ensure systems function seamlessly in real-world applications. Siemens’ Stephen V. Chavez finds that ultra high-density interconnect (UHDI) has changed the design and production of PCBs to enable ... » read more

2D Semiconductors Make Progress, But So Does Silicon


Semiconductor industry researchers have been anticipating the need for better transistor channel materials to replace silicon for a long time, but silicon devices have continued to improve enough to postpone that change. Silicon continues to provide an unmatched combination of device performance, manufacturability, and cost effectiveness. In recent years, though, the “end of silicon” cha... » read more

Early Architecture Performance and Power Analysis of Multi-Die Designs


Despite the clear advantages of multi-die designs, there are numerous new challenges that stand in the way of multi-die design realization. This white paper focuses on those challenges that can be addressed by early architecture exploration of multi-die designs, including: -System pathfinding -Memory utilization and coherency -Power/thermal management Find out how to overcome such chall... » read more

← Older posts Newer posts →