Bringing RFIC Design And Verification Into The Modern Era

Achieving optimal RF designs while minimizing turnaround time.


For decades, developers of radio frequency (RF) chips and other analog/mixed-signal (AMS) integrated circuits (ICs) have used traditional techniques for design and verification. Most RFIC designers have continued to hand-craft active and passive devices, manually place and route their circuits, and rely on the bring-up lab to validate their pre-silicon SPICE simulations. It is often said that analog design is as much an art as a science, but even the cleverest manual techniques take time and effort that may compromise project cost and schedule. Development teams are finding that legacy flows are insufficient to meet the needs of modern RF designs. Today’s RFICs are complex chips by themselves, and hyperconvergence is combining RF, analog, and digital logic into single devices. This convergence exacerbates systemic complexity and drives the need to rethink RFIC design and verification. Frequency of operation is also moving upward from low-GHz to millimeter wave frequencies, further complicating the RFIC design and verification.

Higher levels of integration at higher frequencies put a lot of pressure on analog and RF teams to “shift left” their design and verification process. A modern RFIC development flow must shorten the turnaround time (TAT) for each design iteration while still achieving the best possible circuit performance. Further, many RF circuits are used in applications where high safety and reliability are critical for the entire silicon lifecycle. For example, an autonomous vehicle has no chance of driving safely if the real-world data arriving from its sensors is corrupted due to failures induced by electro-thermal stress, variations and defects in the chip manufacturing process, or aging silicon.

There are many requirements that must be met by any viable modern RFIC design and verification solution. It must support all leading IC technologies, including finFET, planar CMOS, SOI, and SiGe. Process development kits (PDKs) for these technologies must be developed in close collaboration with chip vendors. Advanced schematic and layout editing features must be automated efficiently to reduce repetitive and manual work in creating and interconnecting components. It must be possible for designers to customize transistors and inductors for superior RF performance since off-the-shelf library devices may not meet the needs of the most advanced designs. To reduce design time, the solution must be capable of synthesizing passive RF devices such as single-ended and differential inductors, T-coils, and transmission lines.

The nature of RFIC development is highly iterative, with the designer making changes in the design, running simulations and other forms of analysis, and tweaking the layout to improve the results. Reducing the TAT for each iteration requires faster layout creation plus excellent simulation performance. RF circuits containing LNA, switch, PA, mixer, and VCO elements need fast harmonic balance simulation. Speedy transient simulation is also mandatory, especially for full transceivers and PLLs that include RF, analog, and digital circuitry. Shorter TAT, accelerated verification closure, and faster RF signoff require a unified workflow of advanced circuit simulation technologies and seamless integration of electromagnetic and layout parasitic extraction.

Reliable and robust RFIC designs spanning the full silicon lifecycle demand several additional capabilities. As the circuit layout evolves, physical verification must be fast and accurate, with built-in checks for electromigration (EM), IR-drop, and electrostatic discharge (ESD) issues. Additional required checks include:

  • Device self-heating and circuit analysis
  • High-sigma Monte Carlo analysis with process variations
  • Full set of corners including the process corners in combination with the electromagnetic model corners for passive components and interconnects

Not surprisingly, developing an RF design and verification solution that meets all these requirements has been a huge hurdle for the electronic design automation (EDA) industry. Different requirements have been addressed at various times, and often multiple EDA tool vendors have been involved. Users frequently have had to cobble together disjointed pieces, resulting in suboptimal performance, schedule, and reliability gains. In parallel, the need for more tool innovation and a unified solution has grown even stronger. RF design is getting tougher, design schedules remain tight, and advanced nodes offer great opportunities but with major technical challenges. The lack of a single, truly innovative solution has kept RFIC designers from moving fully into the modern era.

The world of RF design and verification has been revolutionized by Synopsys custom design products such as PrimeSim Continuum simulation, Custom Compiler schematic and layout, and IC Validator verification tools that accelerate the development of robust RF, AMS, and full-custom digital designs. PrimeSim SPICE not only has a 10X faster transient simulation engine, but also an advanced Harmonic Balance (HB) engine that simulates pre-layout and post-layout RFICs much faster. Custom Compiler visually assisted layout automation and layout reuse with template provide 10X faster layout. Electromagnetic simulators, including VeloceRF and RaptorX from Ansys, and RFPro from Keysight, are seamlessly integrated into Custom Compiler.

This cohesive, comprehensive solution meets all the requirements for modern RFIC development, reducing TAT, yielding high-performance designs, and supporting applications with a high bar for safety and reliability. Key requirements covered include passive RF device synthesis, multi-function analysis within a single tool, and a wide range of built-in checks. The tools offer additional unique capabilities that make RF design and verification more efficient and more accurate. This starts with circuit layout, which benefits from both advanced visual editors and intelligent assistants for placement, routing, and track planning. Designers can leverage a built-in template library or create and use new templates.

Optimal design with minimal TAT is achieved by numerous fast RF simulation and analysis options. These include best-in-class transient simulation, harmonic balance and envelope simulations, noise analysis, Monte Carlo analysis, aging analysis, and support for 2.5D/3DIC designs. A unified 3D fast field solver provides gold-standard device parasitic extraction and symmetric net extraction. Design rule checking (DRC) and electromigration and IR-drop (EMIR) checking are performed during layout to reduce post-layout simulation surprises and minimize signoff iterations. EMIR analysis, coupled with analog fault analysis, ensures the reliability of safety-critical circuits. This entire flow is available for a wide range of processes and technologies, using PDKs developed by working closely with foundry partners such as TSMC, Samsung, and GlobalFoundries.

Currently deployed in production usage, Synopsys custom design tools move RF design and verification into the modern IC era and beyond. Design from schematic to layout occurs up to five times faster than with traditional manual flows and typical design closure time is cut in half, all while maintaining golden levels of accuracy. RFIC engineers can finally benefit from a modern design and verification flow while creating optimal designs. For further information, please visit

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