Build It Faster

The race is on to shrink market windows even further. That will force enormous changes across the supply chain.

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By Ed Sperling
Hitting market windows with IC designs has always been a struggle, but the race to the finish line is becoming more critical—and much more difficult. The reason: Market windows themselves are shrinking.

Products that used to stick around for years may now only last for months, replaced by newer versions that offer either better performance or lower power. In many cases, particularly for the hottest consumer markets that drive the highest volumes, there isn’t even time for competing on cost with derivative chips. The so-called long tail of design now looks significantly shorter, overtaken by a quick ramp up to the next SoC.

This raises a slew of new concerns among chip designers about which market opportunities are worth the risk, at which process node, and how to get there quickest with the least amount of risk. It also raises issues among tools developers about how many customers there will be for tools if the largest customers skip process nodes. And it raises the stakes across the board for making bad decisions, because they can no longer be amortized across dozens of derivative designs.

Changing market dynamics
What’s behind much of this is a shift in consumer buying habits. It’s not that consumers necessarily buy more devices, but they buy them much more quickly after the release date. The iPhone 4S was a classic example. Within four days of its introduction sales had topped 1 million units, something that took years for previous product lines.

“We used to be able to use a shotgun approach,” said Mike Gianfagna, vice president of marketing at Atrenta. “Now it’s more like a precision rifle shot. And if you don’t hit it just right, the market is gone.”

Time-to-market has escalated from important to critical. But for most companies that also involves a disaggegrated supply chain, which tends to slow down the design process more compared with IDMs such as Intel and Samsung, which have regular communications between fab, design teams and debug operations.

“What we’re heading toward is virtual re-aggregation,” said Gianfagna. “But that’s going to require speed and perfection, a lot of standards, and changes throughout design.”

It also changes the rules about how companies go to market with new ideas and technology.

“Traditionally, people went into market to test the waters,” said Neil Hand, group marketing director for Cadence’s SoC Realization Group. “The way things are now, you have to get it right. And if you’re successful, you have to quickly turn out new products. Product planning is important, but you also have to build in flexibility.”

Multi-patterning, packaging, and physics
It also requires some techniques and approaches that were not even considered in the design process until very recently. Sequential flows are now concurrent, with manufacturing now an important element of the early design phase. One area that is a particular trouble spot involves lithography, where EUV has been considered the best hope for etching extremely thin lines. EUV was expected to be commercially viable years ago. It’s still in the development stage, which is why the industry is heading to double patterning at 22/20nm. And that slows down the whole process significantly.

“Double patterning means you’re splitting a single mask up into two masks,” said Wally Rhines, chairman and CEO of Mentor Graphics. “And at 14nm we’re still uncertain whether the solution will be EUV or triple patterning. It could be either one. It depends on the development schedule of EUV. We may have a node that starts out without EUV and ends up with EUV. From the perspective of power and throughput it’s still a long way from production-worthy. The backup is triple patterning. It’s undesirable from a cost point of view.”

For an industry that has banked heavily on proven techniques and processes, this is a remarkably untested future with a very uncertain throughput and cost structure, filled with a variety of other risk factors.

Stacking of die will complicate that further, because understanding the stress impact of TSVs remains fuzzy, at best. Interposers are slightly better tested, particularly more advanced versions that potentially use new materials. In addition, wide I/O standards are still being developed, and so are ways of connecting all the pieces together, testing and debugging them, and figuring out how to deal with heat dissipation.

There’s also a question about what will get valued most in this new approach—and where the development dollars will go for tools. That also can affect time to market, because if the tools aren’t updated or integrated companies will have to do that work themselves—something they’ve done in areas such as rapid prototyping until recently, when commercially integrated solutions became available.

“It’s a little like the automotive or aircraft industry,” said Rhines. “The people who put the pieces together are system integrators. They deal with multiple die. They deal with software. They deal with interconnects. They are system designers. Then the individual die, an the individual IP, are component suppliers to each other. Today that IP serves as a barrier, but it will commoditize. System integrators get paid more than component suppliers, and components become commodities.”

Unbundling and future changes
One way to facilitate these kinds of changes is by unbundling the individual pieces in an SoC.

“There are really relatively few new hardware blocks being added to new designs,” said Drew Wingard, chief technology officer at Sonics. “The exception is the continued improvement in processor cores from ARM or graphics engines. Mostly it’s continued pressure on integration, and we believe strongly the only way to deal with this effectively is to isolate the components.”

He noted that interdependencies make it difficult to advance one component in a package without also making changes to another component. That has proven particularly problematic for mixed signal blocks, where shrinkage of digital features has forced similar but extremely painful shrinkage of analog processes. By separating those worlds, progress can be made in both portions of the block when it makes sense.

“If you can decouple the verification you can divide and conquer,” said Wingard. “That allows you to do verification at the subsystem level and re-use testbench code. A lot more companies also are thinking about designs in a platform-based way. A platform is a set of decisions you’ve made, and then you abstract up and down.”

Platforms have been talked about for years as a future direction. Intel, which used to churn out dozens of different chips for various PC markets, adopted a platform approach with the introduction of its Core architecture. ARM has done the same with its Cortex line. And while SoC developers have had a much more difficult time with this approach, many of components within those chips are developed using a platform approach.

But every decision has ramifications in an SoC. While it’s okay to unbundle the components, everything is tied to everything else in ways that extend well beyond the chip.

“When you develop a chip in the wireless space you have to make sure you’re in sync with the carriers, the handset makers, and the whole value chain,” said Kurt Shuler, director of marketing at Arteris. “This becomes a problem when you start shrinking the design time. It used to take 18 to 24 months to gather requirements to put a chip out there. Now the best designs take 9 to 12 months, and the most advanced companies are pushing to get that down to 6 to 9 months. The only way to do that is with a platform approach where you have one hardware and software platform and you can re-use the hardware and software investment.”

Re-use is driving a significant portion of Synopsys’ business these days. It’s no longer just IP blocks that are being sold. It’s IP plus software, and often in conjunction with services.

“We absolutely believe the next major evolution is subsystems of larger integrated blocks,” said John Koeter, vice president of marketing for Synopsys’ Solutions Group. Those subsystems increasingly are customized for very specific markets, as well, to both reduce risk and decrease the time it takes to get an SoC out the door. “These are very market-specific, he said. In the audio area an MP3 will have codecs that are different from a home entertainment system. We’re also seeing an increased willingness among companies to outsource. It’s not just small companies, either. It’s also the big tier-one companies that are questioning whether a USB is differentiating their chip.”

The push for more standards
Platforms also require standards, and there is mounting pressure on all of the standards bodies to ramp up the number and quality of standards—and to avoid dual standards such as UPF and CPF. But hidden in all of this also is a recognition that vendors will have to pick their battles. They can’t compete on all fronts and still have progress in standards.

“Standards are created largely around efficient ways of exchanging data in design and manufacturing,” said Steve Schulz, president and CEO of Si2. “If you had to re-do models for every foundry chip that would quickly get out of scale. Standards allow companies to get to market faster.”

That becomes more difficult in stacked, however, which involves more companies from across the supply chain. The promise of stacked die is re-usability, possibly with entire logic or analog “platforms” as part of the stack.

“Everything about 3D is a supply-chain view,” said Schulz. “You need to understand the whole landscape to do anything in 3D. How do you describe hot spots on a die? What’s the basic connectivity between the package and the pins? How are you going to develop the interposers? If you create process design kits will they need to understand the process impact of TSVs? And when is all of this going to happen? We’re not sure about the time frame.”

Conclusions
Dealing with time-to-market pressures has always been a concern, but rarely did being late to market mean missing out on the market entirely. That reality is changing, however, putting pressure on teams to figure out ways to ensure quicker turnarounds with better results.

Software, in particular, is a problem that needs to be dealt with effectively. As Cadence’s Hand says, “We need to bring down design and manufacturing costs, but software is still the killer.”

To some extent this is likely to force some hiring in the industry. Companies never replenished their ranks after laying off engineers in 2008. It also will require more tools, because automation is much faster in the hands of trained engineers than spreadsheets and trial and error. And it will require renewed cooperation to push through standards in areas where companies can agree it’s not necessary to compete—or where competition may slow down entire markets.

These changes also are likely to reshape the IC industry in ways we cannot even begin to comprehend at the moment. At the base of all of this is a fundamental and global shift that time to market will no longer be determined from the bottom up. It will be driven from the top down—by the consumers of the technology who are willing to spend quickly and decisively rather than mulling purchases for months or years. The winners will be those that can figure out a way to meet that need—and the losers will be either quickly absorbed or, worse, forgotten.