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Cache Coherence In Network On Chip Design (NTU)

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A new technical paper titled “Learning Cache Coherence Traffic for NoC Routing Design” was published by researchers at Nanyang Technological University.

“In this work, we propose a cache coherence-aware routing approach with integrated topology selection, guided by our Cache Coherence Traffic Analyzer (CCTA). Our method achieves up to 10.52% lower packet latency, 55.51% faster execution time, and 49.02% total energy savings, underscoring the critical role of cache coherence in NoC design and enabling effective co-design,” states the paper.

Find the technical paper here. April 2025.

arXiv:2504.04005v1
https://doi.org/10.48550/arXiv.2504.04005
Authors: Guochu Xiong, Xiangzhong Luo, Weichen Liu



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