category: A Bit About Memory

category: IoT, Security & Automotive

PCIe 4.0 Hangs In, PCIe 5.0 Coming On Strong
By Mondeep Thiara - 17 Jan, 2019 - Comments: 0

First introduced in 2003 as a universal serial chip-to-chip interface running at 2.5 Gbps, PCI Express (Peripheral Component Interconnect Express), also known as PCIe, has advanced several revisions with significant improvements to performance and other features with each new generation. Through broad support, backwards compatibility, and a consistent cadence of upgrades that doubled lane sp... » read more

Taking Steps Toward Hybrid Memory
By Ken Wright - 13 Dec, 2018 - Comments: 0

What is the memory subsystem of the future, and how do we get there? Since our Hybrid Memory research program began, Rambus Labs and its industry partners and collaborators have made significant progress under the banner of OpenPOWER and OpenCAPI Foundations, an open development community based on the POWER microprocessor (mP) architecture. Rambus Labs is using the Wistron POWER9 systems’ Ope... » read more

Die-to-Die Interconnects for Chip Disaggregation
By Mondeep Thiara - 10 Nov, 2018 - Comments: 0

Today, data growth is at an unprecedented pace. We’re now looking at petabytes of data moving into zettabytes. What that translates to is the need for considerably more compute power and much more bandwidth to process all that data. In networking, high-speed SerDes PHYs represent the linchpin for blazing fast back and forth transmission of data in data centers. In turn, demand is increa... » read more

Die-To-Die Interconnects For Chip Disaggregation
By Mondeep Thiara - 09 Nov, 2018 - Comments: 0

Today, data growth is at an unprecedented pace. We’re now looking at petabytes of data moving into zettabytes. What that translates to is the need for considerably more compute power and much more bandwidth to process all that data. In networking, high-speed SerDes PHYs represent the linchpin for blazing fast back and forth transmission of data in data centers. In turn, demand is increasin... » read more

ADAS Further Extends 7nm Challenges
By Mondeep Thiara - 11 Oct, 2018 - Comments: 0

As we discussed previously on the LPHP blog, 7nm nodes hold great promise for reducing power, improving performance and increasing density for next-generation chips, but also present a set of engineering challenges. When you factor in the standards set for autonomous vehicles (AV) and advanced driver assistance systems (ADAS) system-on-chips or SoCs, those challenges can more than double. Autom... » read more

High-Performance Memory At Low Cost Per Bit
By Liji Gopalakrishnan - 09 Aug, 2018 - Comments: 0

Hardware developers of deep learning neural networks (DNN) have a universal complaint – they need more and more memory capacity with high performance, low cost and low power. As artificial intelligence (AI) techniques gain wider adoption, their complexity and training requirements also increase. Large and complex DNN models do not fit on the small on-chip SRAM caches near the processor. This ... » read more

5G Wireless Infrastructure Pushes High-Speed SerDes Protocols
By Mondeep Thiara - 14 Jun, 2018 - Comments: 0

5G is the 5th generation wireless system standard that, through high speeds and increased accessibility, promises to change the way we stream, communicate, work, and travel. Boasting speed capabilities of 20Gbps and network densities of 1 million connected devices per square kilometer, 5G is the required technology for the implementation of highly anticipated technologies like autonomous vehicl... » read more

Deep Learning Neural Networks Drive Demands On Memory Bandwidth
By Frank Ferro - 10 May, 2018 - Comments: 0

A deep neural network (DNN) is a system that is designed similar to our current understanding of biological neural networks in the brain. DNNs are finding use in many applications, advancing at a fast pace, pushing the limits of existing silicon, and impacting the design of new computing architectures. Figure 1 shows a very basic form of neural network that has several nodes in each layer that ... » read more

Navigating The Foggy Edge Of Computing
By Aharon Etengoff - 12 Apr, 2018 - Comments: 0

The National Institute of Standards and Technology (NIST) defines fog computing as a horizontal, physical or virtual resource paradigm that resides between smart end-devices and traditional cloud or data centers. This model supports vertically-isolated, latency-sensitive applications by providing ubiquitous, scalable, layered, federated and distributed computing, storage and network connecti... » read more

How AI Impacts Memory Systems
By Steven Woo - 08 Mar, 2018 - Comments: 0

Throughout the 1980’s and early 1990’s computer systems were bottlenecked by relatively slow CPU performance, thereby limiting what applications could do. Driven by Moore’s Law, transistor counts increased significantly over the years, improving system performance and enabling exciting new computing possibilities. Although computing capabilities have advanced significantly in recen... » read more

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