category: Best Of Both: LP & HP

category: IoT, Security & Automotive

Best Practices
By Tom Fitzpatrick - 14 Mar, 2013 - Comments: 0

By Tom Fitzpatrick Active power control management for low-power designs has become a hot topic, especially with the latest update to the Unified Power Format standard. Version 2.1 was approved by IEEE on March 6, 2013. UPF gives the ability to specify power control for different parts of a design, separate from the RTL itself. The advent of low-power design has greatly increased the comple... » read more

Leakage Optimization
By Arvind Narayanan - 24 Feb, 2013 - Comments: 0

By Arvind Narayanan For consumer electronics such as cell phones, tablets, and laptops, long battery life is a key requirement. Battery life is directly related to total power consumption—which is a function of switching activity, capacitance, and voltage—across all operational modes. In full active mode on a cell phone, for example, the dynamic power that comes from signal switching is hi... » read more

Guidelines For Designing Multi-Voltage ICs
By Arvind Narayanan - 17 Jan, 2013 - Comments: 0

By Arvind Narayanan Multi-voltage designs are increasingly common in ICs for mobile devices, but can be difficult to implement. The design flows for multi-voltage architectures are inherently complex and present many new challenges because many blocks are either operating at different voltages or are shut down intermittently. Multi-threshold CMOS switches enable switching off certain portio... » read more

The Next UPF
By Erich Marschner - 06 Dec, 2012 - Comments: 0

By Erich Marschner If all goes according to schedule, the new version (2.1) of five-year-old Unified Power Format (UPF) standard will be approved by the IEEE early next year. This is good news, because in the five years since UPF was first defined the demand for systems with both longer battery life and more functionality has increased significantly. As just one example: according to Gartner, ... » read more

The Trouble With Clock Trees
By Arvind Narayanan - 11 Oct, 2012 - Comments: 0

By Arvind Narayanan Among the perennial challenges of advanced-node IC design is power reduction. Clock trees are now the single largest source of dynamic power consumption, which makes clock tree synthesis (CTS) and optimization an important task for achieving overall power savings. Building a well-balanced clock tree and effectively managing clock skew has been a challenge since the first... » read more

Improving Reliability
By Dina Medhat - 13 Sep, 2012 - Comments: 0

By Dina Medhat Advanced IC designs implement complex strategies to minimize static and dynamic power. Mixed-signal designs typically require different supply voltages for the analog and digital portions of the design, and even all-digital ICs can have many power domains and operating voltages. Typically, some signal lines cross from one domain to another and special interfaces and “voltage p... » read more

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