category: Best Of Both: LP & HP

category: IoT, Security & Automotive

Easier Low Power ICs With Reference Flows
By Terence Chen - 09 Jul, 2020 - Comments: 0

By Terence Chen and Alexander Volkov Power-sensitive ICs for wearables and internet of things (IoT) products are in demand for markets ranging from automotive to military/aerospace to consumer. As with most ICs, cost and time-to-market pressures are important determiners of success. Reducing risk by using a vendor-created reference flow can confer a serious business advantage. Reference f... » read more

Is Common Resistance Affecting Your Analog Design Reliability And Performance?
By Hossam Sarhan - 11 Jun, 2020 - Comments: 0

Integrated circuit (IC) design reliability has always been important and essential to market success. After all, if no one could count on your product to operate as designed, and for as long as intended, there wouldn’t be many buyers! However, given the increase in the types and complexity of design applications, coupled with the increasing technological challenge of manufacturing at advance... » read more

Power Management And Integration Of IPs In SoCs: Part 2
By Progyna Khondkar - 14 May, 2020 - Comments: 0

Most IP are available as either soft or hard macros. But both pose immense challenges. This is especially so when integrating them into low power designs and conducting power aware (PA) verification, because the majority of IP are self-contained and pre-verified at the block level and they must be preserved in their entirety when integrated or verified in the SoC level. Part one of this two ... » read more

Power Management And Integration Of IPs In SoCs: Part 1
By Progyna Khondkar - 09 Apr, 2020 - Comments: 0

IPs – whether in the form of soft or hard macros – are the epicenter of today’s SoC designs. Integration of IP with low power designs and conducting power aware (PA) verification are always complex and cumbersome. Because most of these IPs are self-contained, pre-verified at the block level, and must be preserved in their totality when integrated or verified at the SoC level. Until UPF... » read more

Aging Analysis Standard Solidifies Through Collaborative Effort
By Ahmed Ramadan - 12 Mar, 2020 - Comments: 0

By Ahmed Ramadan, Greg Curtis, Harrison Lee, Jongwook Kye, and Sorin Dobre We live in a connected world and it is estimated that by 20251 the total amount of worldwide data will swell to 163 ZB, or 163 trillion gigabytes. This rapid growth in data expansion is driving an explosion in new designs and new requirements for consumer, data center, automotive, and Internet of Things (IoT) applicat... » read more

Earlier Is Better In Latch-Up Detection
By Flint Yoder - 13 Feb, 2020 - Comments: 1

Physical verification is an essential step in integrated circuit (IC) design verification. Foundries provide design rule manuals that specify the precise physical requirements needed to ensure the design can be correctly manufactured, and the verification team runs the layout through checks based on those rules to ensure compliance. However, ensuring that a design can be manufactured does not g... » read more

Three Steps To Faster Low Power Coverage Using UPF 3.0 Information Models
By Madhur Bhargava - 16 Jan, 2020 - Comments: 2

Controlling power has its costs. The added power elements and their interactions make verification of low-power designs much more difficult and the engineer’s job overwhelmingly complex and tedious. Early versions of the Unified Power Format (UPF) provided some relief, but lacked provisions for a standardized methodology for low-power coverage. Ad hoc approaches are error prone and highly ... » read more

Optimizing Power And Performance For Machine Learning At The Edge
By Mike Fingeroff - 12 Dec, 2019 - Comments: 0

While machine learning (ML) algorithms are popular for running on enterprise Cloud systems for training neural networks, AI/ML chipsets for edge devices are growing at a triple digit rate, according to Tractica “Deep Learning Chipsets” (Figure 1). Edge devices include automobiles, drones, and mobile devices that are all employing AI/ML to provide valuable functionality. Figure 1: Marke... » read more

Three Steps To Complete Reset Behavior Verification
By Chris Kwok - 14 Nov, 2019 - Comments: 0

By Chris Kwok, Priya Viswanathan, and Ping Yeung Reset architectures are notoriously complex and difficult to verify. Today’s SoCs contain highly complex reset distributions and synchronization circuitry. Often, reset trees can be larger than clock trees and have many of the same potential issues. Verifying that a design can be correctly reset under all modes of operation presents signi... » read more

Seeing Is Believing: Visualizing Full Coverage Closure In Low-Power Designs
By Madhur Bhargava - 10 Oct, 2019 - Comments: 0

By Madhur Bhargava and Durgesh Prasad Lowering the power consumption and leakage in SoCs and other electrical designs has become a paramount concern in recent years. The reasons for this are many and well understood. The structures and techniques we use to accomplish this have made verification of so called low-power designs more complex and difficult than it is for designs where power usage... » read more

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