Earlier Is Better In Latch-Up Detection

Physical verification is an essential step in integrated circuit (IC) design verification. Foundries provide design rule manuals that specify the precise physical requirements needed to ensure the design can be correctly manufactured, and the verification team runs the layout through checks based on those rules to ensure compliance. However, ensuring that a design can be manufactured does not guarantee that the circuitry it creates will operate as designed.

For that assurance, a design company’s experts create additional rules to check circuit functionality and confirm that their products will be functional and reliable in operation. Each electrical rule check (ERC) typically checks for the existence of a specific failure scenario that will cause the IC to either be non-functional or fail during operation.

One of the challenges of ERC is that electrical failure situations can actually be created as a result of the manufacturing process, so engineers must craft rules that look for conditions that will potentially lead to the formation of these failure mechanisms. For example, a condition known as latch-up has long been a source of frustration for circuit verification engineers. Although the detection of latch-up vulnerability has been heavily researched, it is created by a complex combination of factors, making it difficult to identify early in the design flow when using traditional verification tools. However, finding and preventing latch-up conditions early in the design process not only helps prevent costly design changes late in the schedule, but also contributes to higher product reliability, making latch-up vulnerability detection a prime target during circuit verification. Adopting automated latch-up verification that can be used during schematic design enables designers to more easily detect and accurately mitigate latch-up conditions before layout implementation.

What is latch-up?
A latch-up condition occurs within a design when an unintentional structure, which can be either a thyristor or a silicon-controlled rectifier (SCR) formed through the parasitic elements of the IC, is triggered and becomes locked (latched) into an on state [1]. Devices within an IC reside either within P-doped or N-doped regions of silicon. Because these oppositely-doped regions are alternated within the IC layout, parasitic PNP and NPN transistors sometimes form within the substrate of the chip itself.

Figure 1 shows a classic latch-up failure scenario. When a sequence of four doped regions (NPNP or PNPN) is present in a layout, these unintentional transistor elements form either a parasitic thyristor or SCR, as shown in Figure 1. Given the correct stimulus, this parasitic element can be triggered to an on state, and will continue to feed itself such that it remains latched. Once a thyristor or SCR is latched, it can only be unlatched by removing the forward bias voltage on the parasitic device.

Fig. 1: SCR cross-section showing parasitic coupling between diffusions connected to VDD and VSS [1].

A latch-up event alters the intended behavior of the circuit affected by the parasitic device, causing loss of functionality (and in some cases, permanent damage to the IC) [2]. Due to the severity of latch-up failures, designers exert all possible efforts to avoid creating design conditions that allow latch-up scenarios to occur.

Unfortunately, the unpredictable nature of the latch-up event makes it difficult to detect latch-up susceptibility during product design and verification. Unlike other problem scenarios addressed by ERC verification, latch-up isn’t caused directly by the connectivity of the circuitry within the design. Instead, it is interrelated to both the circuitry and the physical aspects of how the parasitic thyristor or SCR is created within the IC layout. This is particularly true when various intellectual property (IP) blocks used within a layout might be immune to latch-up by themselves, but create latch-up susceptibility when placed near each other.

Latch-up detection and prevention

Traditional latch-up protection
As mentioned earlier, latch-up is not a new phenomenon within the IC design industry, and the detection of latch-up vulnerability has been heavily researched. The result of this research was a set of layout design guidelines design teams can follow to mitigate the risk of latch-up events.

For a parasitic thyristor to be triggered, sufficient current must be injected, either directly into the thyristor’s terminal or into the nearby substrate, and the holding voltage of the thyristor must be met. Two main detection methodologies exist, both of which address the root cause of the latch-up event (the triggering of the parasitic thyristor element), but from different angles. The design rules used to validate a layout for latch-up immunity require either a large spacing between N-type and P-type structures, or the placement of an efficient guard ring structure (e.g., a pair of guard rings, or even multiple sets of P-type and N-type guard rings) between the two.

Spacing protection
The spacing methodology used to prevent parasitic thyristors from triggering works by increasing the magnitude of the event current required to latch the device [2,3]. Because the silicon is resistive, increasing the spacing between N-type and P-type doped regions within the layout means increasing the amount of current that must be injected into the substrate for the parasitic device to reach its latching condition. Foundries typically provide spacing guidelines within their design rule manual (DRM) to avoid latch-up failures. The values provided within these rules identify a safe distance under a given stimulus scenario for the specific manufacturing process addressed by the DRM. These guidelines are enforced like design rules by running traditional DRC software to ensure all related layers meet these spacing requirements.

Guard ring protection
The guard ring method places guard rings around N-type and P-type structures (such as transistors, diodes, and their associated N- or P-type wells). The basic form of a guard ring is a surrounding ring of supply-tied metal that acts to collect some of the substrate current [4]. If enough of the current is absorbed by the guard ring, the remaining amount is insufficient to trigger the parasitic thyristor. There are several factors that determine how efficient a guard ring is in absorbing the substrate current, including the width of the guard ring, and the level of parasitic resistance on the path between the ring and the supply to which it is tied [3].

The stumbling block with both of these verification solutions is that they require a high level of layout completion to comprehensively check for latch-up scenarios within the design, meaning latch-up validation is traditionally completed as one of last stages before final signoff. At this point, any latch-up error condition identified will require layout spacing changes or the addition of guard ring structures. As every designer knows, late-stage design changes can lead to complicated and time-consuming rerouting. In extreme cases, it might not even be possible to accommodate the required changes within the allotted design area.

Making the job of detection and removal that much harder, increased design complexity and process scaling both increase sensitivity to latch-up [3,4]. To avoid expensive and time-consuming late-stage re-design scenarios, design teams need a latch-up validation solution that can be applied earlier in the design flow, before changes become exorbitantly expensive and affect tapeout schedules.

Topology-driven latch-up protection
Traditional layout-based methods strive to provide sign-off level assurance that no latch-up conditions exist in the layout, based on the physics of a latch-up event and the known physical parameters of the design. But as we’ve just seen, using traditional DRC-style latch-up validation in the post-layout design stage means restructuring or rerouting the design, which is difficult and costly.
To implement latch-up checking and make design changes during earlier stages of the design flow, latch-up design rules must operate on schematic data, well before layout implementation is completed. Performing latch-up detection during schematic design, rather than post-layout signoff, allows sensitive structures to be identified and the knowledge of their latch-up sensitivity used to influence how the design is put together. There are several scenarios that can be identified through topological checks alone that denote high latch-up susceptibility. By focusing verification efforts on these scenarios during early design stages, designers can actively remove or mitigate them before any layout routing is completed.

One sensitive scenario is the presence of MOS devices with direct (low resistance) connections to I/O ports [2]. This so-called “hot” connection allows a carrier injection event to more easily reach the parasitic thyristor that may be formed between the I/O-connected MOS device and any surrounding circuitry at a strength level that can trigger latch-up. By identifying the hot connection during schematic design, designers can add a series resistor to greatly reduce the latch-up susceptibility of all the surrounding circuitry. This not only prevents the latch-up failure, but also allows more flexibility in layout routing, due to less stringent spacing requirements.

A second scenario is the presence of structures that make use of grounded or biased N-wells. The parasitic thyristors formed from these wells have different trigger and holding properties, and are (in general) more sensitive to latch-up than alternative well structures [2,4]. While these susceptible wells only exist within the layout, there are some devices that typically make use of these well structures (such as certain capacitors and diodes) that can be identified in the schematic netlist through topological analysis. The function of these devices may be needed to create a functional IC, but where possible, design teams can make use of less-sensitive elements (like transistors) to achieve the same function while eliminating the high latch-up sensitivity.
Another factor in latch-up susceptibility is the operating voltage of the involved circuitry. Higher voltages and drive strength create greater potential to trigger a parasitic thyristor [5]. Properly identifying circuitry that will be problematic requires an understanding of net and device voltages to correctly report all true error conditions, while avoiding false errors that require time-consuming manual review.

The best case outcome for any potential latch-up scenarios identified by topological analysis is to alter the design such that the condition no longer exists. However, even when design requirements or constraints make it impossible to remove or alter the offending circuit, early detection still provides a massive benefit over traditional latch-up verification approaches. In these cases, topological analysis provides an early warning that this portion of the IC requires extra care during the layout design phase. Because this knowledge is available prior to layout implementation, designers can proactively place these circuits with maximum spacing, place them far away from other sensitive structures within the layout, or include guard rings. What would have been an expensive rerouting process can be avoided through early schematic identification of potential latch-up failures.

Automated latch-up verification with topological analysis
Specialized reliability verification EDA tools are available that provide a robust and efficient topological analysis engine designers can use to automatically identify nets and devices of interest on any design, both for schematic netlists and layout databases. By using automated static voltage propagation to identify the voltages throughout a design schematic, such tools can combine the resulting voltage information in conjunction with latch-up rule checks to identify circuitry that may contain or result in structures susceptible to latch-up. Figure 2 shows the automated static voltage propagation process of the Calibre™ PERC™ reliability platform from Mentor, a Siemens business.

Fig. 2: Specialized EDA tools like the Calibre PERC platform can assign voltages to all internal nodes of the IC in an efficient static process, then use this information in combination with latch-up design rules to detect potential latch-up conditions early in the design flow.

When a susceptible condition is found, such tools can automatically apply the appropriate constraints to any portion of a design, based on the voltages found on the nets and device pins in that section, without running SPICE simulations or drawing marker layers within the layout. This process provides assurance that highly sensitive areas are checked against worst-case constraints, while allowing less-sensitive areas to use layout area that would otherwise be wasted in unnecessary protective spacing.

This programmatic approach enables designers to easily and accurately analyze all design elements and handle the nuances of their design methodologies. By running automated latch-up verification early and often during the schematic design phase, designers can be confident that each element and interaction within a design has been checked, and potential latch-up scenarios have been identified. Once identified, this information can be shared with other design teams, giving them ample time to implement mitigation before a failure scenario is created. The end result is an IC that is designed from the beginning with latch-up resistance in mind. Latch-up verification can then be run during the post-layout stage to provide sign-off level validation for the chip, with a high level of confidence that few or no latch-up conditions will be identified.

Conclusion
The need for high-reliability components is ever-present and growing across all of today’s IC market segments. Latch-up is a critical failure condition that can downgrade performance or lead to total IC failure. Traditional latch-up detection occurs late in the design flow, requiring costly and time-consuming late-stage physical layout changes. By running automated topology-based latch-up verification on the schematic netlist during early design phases, designers can quickly identify sensitive latch-up scenarios. Most of these latch-up conditions can be quickly resolved through circuit design changes without any major impact on IC implementation, preventing expensive delays and emergency rerouting. When potential failure conditions cannot be eliminated, early identification of latch-up sensitive elements placed within or created by the design circuitry allows designers to mitigate any potential failure by making informed decisions during later chip development. Automated latch-up verification can also be run during the post-layout stage to ensure the full chip is protected against performance degradation and product failure. With this multi-stage approach, automated topology-based latch-up verification provides a comprehensive, efficient, automated, and reliable way for IC design teams to find and prevent latch-up failure scenarios before they require costly design changes that delay the tapeout schedule.

With the spread of electronics into critical infrastructure such as transportation, power generation and delivery, aerospace and military, and medical devices, failure is not only undesirable, it is simply not an option. Implementing an efficient and accurate automated latch-up verification flow can help design companies deliver products that meet the high performance and reliability standards of today’s markets, while using the most efficient and cost-effective means possible.

References
[1] A. Oberoi, et al., “Latch-up characterization and checking of a 55 nm CMOS mixed voltage design”, Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2012, Tucson, AZ, 2012, pp.1-10. https://ieeexplore.ieee.org/document/6333300
[2] M. Khazhinsky, et al., “EDA approaches in identifying latchup risks,” 2016 Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), Garden Grove, CA, 2016, pp. 1-11. https://ieeexplore.ieee.org/document/7592552/
[3] M. Ker, et al., “Layout verification to improve ESD/latch up immunity of scaled-down CMOS cell libraries,” Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334), Portland, OR, USA, 1997, pp. 125-129. https://ieeexplore.ieee.org/document/616991/
[4] K. Domanski, “Latch-up in FinFET technologies”, 2018 IEEE International Reliability Physics Symposium (IRPS), Burlingame, CA, pp. 2C.4-1-2C.4-5. https://ieeexplore.ieee.org/document/8353550/
[5] T. Mitchell, et al., “HV latchup—power analog ICs co-design with block level verification,” 2017 Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), Tucson, AZ, 2017, pp. 1-10. https://ieeexplore.ieee.org/document/8073434/