The Seven Pillars Of IC Package Physical Design


Today’s heterogeneously integrated semiconductor packages represent a breakthrough technology that enables dramatic increases in bandwidth and performance with reduced power and cost compared to what can be currently achieved in traditional monolithic SoC designs. Figure 1. A heterogeneously integrated device with 47 chiplets. (Image Source: Intel) The evolving landscape of packagin... » read more

Expecting The Unexpected: Analyzing A Data Center Cooling Failure


Data center thermal management is often a reactive process. Servers issue warning messages, monitoring alarms activate, or employees express concern about general temperature levels/hotspots and then management decides what to do next. For incremental issues, once known, the necessary steps can be taken to resolve or improve these issues; however, what happens when a potential thermal issue onl... » read more

Generative AI On Mobile Is Running On The Arm CPU


By Adnan Al-Sinan and Gian Marco Iodice 2023 was the year that showcased an impressive number of use cases powered by generative AI. This disruptive form of artificial intelligence (AI) technology is at the heart OpenAI's ChatGPT and Google’s Gemini AI model, with it demonstrating the opportunity to simplify work and advance education through generating text, images, or even audio content ... » read more

What Is A Chiplet, And Why Should You Care?


Chiplets are a new way to build system-on-chips (SoCs) that can improve yields and reduce costs by more than 45%. It partitions the chip into discrete elements and connects them with a standardized interface, allowing designers to meet performance, efficiency, power, size, and cost challenges in the 5/6G, AI, and VR era. Unlike monolithic SoCs, chiplets enable an open ecosystem of modular co... » read more

Thanks For The Memories!


“I want to maximize the MAC count in my AI/ML accelerator block because the TOPs rating is what sells, but I need to cut back on memory to save cost,” said no successful chip designer, ever. Emphasis on “successful” in the above quote. It’s not a purely hypothetical quotation. We’ve heard it many times. Chip architects — or their marketing teams — try to squeeze as much brag-... » read more

Impact Of 3DHI On Aerospace And Government Applications


By Ian Land, Kenneth Larsen, and Rob Aitken With challenging size, weight, and power (SWaP) requirements, chip designs for aerospace, defense, and government applications are a unique breed. No surprise here, considering systems like satellites and submarines must operate reliably in the distinctly harsh environments of outer space and ocean depths, respectively. Given the SWaP criteria a... » read more

Is Transformer Fever Fading?


The hottest, buzziest thing bursts onto the scene and captures the attention of the business press and even the general public. Scads of articles and videos are published about The Hot Thing. And then, in the blink of an eye, the world’s attention shifts to the Next New Thing! Are we talking about the latest pop song that leads the Spotify streaming charts? Perhaps a new fashion trend that... » read more

How Can You Use ChatGPT For Software Testing?


All eyes have been on OpenAI and its brainchild ChatGPT in recent months. ChatGPT’s ability to understand and respond to complex instructions and deliver detailed responses to user prompts has led to an explosive rise in its popularity with the public. If you were to search online for “ChatGPT tips,” you can find content to help you use the tool to tailor resumes to job postings, create... » read more

Scaling Server Memory Performance To Meet The Demands Of AI


AI, whether we’re talking about the number of parameters used in training or the size of large language models (LLMs), continues to grow at a breathtaking rate. For over a decade, we’ve witnessed a 10X per year scaling. It’s a growth rate that puts pressure on every aspect of the computing stack: processing, memory, networking, you name it. The platform vendors are responding to the in... » read more

SoC Telemetry & Performance Analysis Using Statistical Profiling Extension


The Arm Statistical Profiling Extension (SPE) is an architectural feature designed for enhanced instruction execution profiling within Arm CPUs. This feature has been available since the introduction of the Neoverse N1 CPU platform in 2019, along with performance monitor units (PMUs) generally available in Arm CPUs. An important step in extracting value from capabilities like SPE and PMUs is th... » read more

← Older posts Newer posts →