category: Blogs – MD

category: IoT, Security & Automotive

Will Directed Self-Assembly Pattern 14nm DRAM?
By Mattan Kamon - 17 Mar, 2016 - Comments: 1

Will directed self-assembly (DSA) join Extreme Ultraviolet (EUV) Lithography and next-generation multi-patterning techniques to pattern the next memory and logic technologies? Appealing to the wisdom of crowds, the organizers of the 2015 1st International DSA symposium recently surveyed the attendees. Nearly 75% believed DSA would insert into high-volume manufacturing within the next 5 years... » read more

The Big Shift
By Ed Sperling - 18 Feb, 2016 - Comments: 0

The number of chipmakers that truly can differentiate their products by moving to the next process node is falling, and that pool will continue to shrink even further over the next few years. Processor companies such as Intel and IBM always will benefit from scaling and architectural changes. So will GPU companies such as Nvidia, and FPGA vendors such as Xilinx, Microsemi and Altera (now par... » read more

Memory Lane: Far From A Leisurely Stroll
By Joanne Itow - 18 Feb, 2016 - Comments: 0

The only semiconductor market segment that has not been taken over by the foundries and still remains dominated by IDMs is the memory sector. The memory market is the last bastion for true IDM manufacturers, who must be savvy in the changing trends in end market applications, advanced technology development, and must still determine how much and when to invest in additional capacity. With on... » read more

When And How Should I Color My DP layout?
By David Abercrombie - 18 Feb, 2016 - Comments: 0

Designers working with advanced process technologies that require double patterning often find themselves puzzling over the best way to setup or optimize their design flows to ensure their layouts can be decomposed without time-wasting mistakes. Because manual coloring can be challenging even for experienced engineers, many prefer to use automated coloring solutions. But when is the best time a... » read more

12 Nations Sign Trade Partnership
By SEMI - 18 Feb, 2016 - Comments: 0

By Taylor Sholler Last week, twelve nations across the Pacific-Rim came together to sign the Trans-Pacific Partnership (TPP) in Auckland New Zealand. These economies, making-up roughly 40 percent of the world's GDP, include Australia, Brunei, Canada, Chile, Japan, Malaysia, Mexico, New Zealand, Peru, Singapore, the U.S., and Vietnam. One of the largest trade agreements in history, the TPP will... » read more

An Insider’s Guide To Planar And 3D DRAM
By Mark LaPedus - 18 Feb, 2016 - Comments: 0

Semiconductor Engineering sat down to talk about planar DRAMs, 3D DRAMs, scaling and systems design with Charles Slayman, technical leader of engineering at network equipment giant Cisco Systems. What follows are excerpts of that conversation. SE: What types of DRAM do network equipment OEMs look at or buy these days? Slayman: When we look at DRAM, we look at it for networking applicatio... » read more

The Economics Of Moore’s Law
By Imec - 18 Feb, 2016 - Comments: 0

By Marc Heyns I’m very optimistic about the continuation of Moore’s Law. But in saying that, I’m speaking about Moore’s Law purely as an economic law. I believe we’ll be able to offer increasing amounts of functionality at lower and lower costs. And technological innovations as well as advances in design and application will be crucial in realizing this. But I don’t believe a ne... » read more

Industry Road Map Under Construction
By Ed Sperling - 21 Jan, 2016 - Comments: 0

While most engineers think in terms of PPA—the classic power, performance and area tradeoffs—their bosses tend to see the world in terms of risk vs. opportunity. Until 22nm, these two objectives moved forward at roughly the same pace, despite the growing technical challenges of fitting more functionality into an SoC. Much has changed since then, and even more will change over the next f... » read more

The Internet Of Power Also Benefits From Moore’s Law
By Imec - 21 Jan, 2016 - Comments: 0

By Jef Poortmans It may sound strange, but striving to achieve smaller dimensions with Moore’s Law is an important enabler for producing increasingly better solar cells, with a more elaborate technology toolbox (including ALD, epitaxy, etc.) Improved process steps are constantly being developed to achieve these small transistor dimensions (for growing material layers or to etch away str... » read more

Automated Power Model Verification For Analog IPs
By Sierene Aymen - 21 Jan, 2016 - Comments: 0

By Sierene Aymen and Hartmut Marquardt Creating macro power models for analog intellectual property (IP) blocks is essential to enable the chip assembly group to effectively integrate these blocks within their place and route environment. These macro models, which define power domains, identify IP ports as signal, power, ground, or trivial ports, and describe the associations of signal pins ... » read more

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