category: Silicon Lifecycle Management

category: IoT, Security & Automotive

Power-Aware Test Vector Porting For Production ATE
By Hari Mani - 12 Nov, 2024 - Comments: 0

Power management in contemporary system-on-chip (SoC) designs is almost unimaginably complex. Processors and other chip cores turn on and off as needed. Advanced features such as dynamic voltage and frequency scaling (DVFS) can adjust to changing conditions and incrementally adjust power and performance on the fly. Power management starts from the lowest hardware level of transistor structures ... » read more

Advancements In Silicon Device Technology And Design Driving New SLM Monitor Categories
By Ash Patel - 15 Oct, 2024 - Comments: 0

Silicon, the foundation of modern electronics, has seen continuous advancements since the early days of integrated circuits. The pace of innovation has been driven by the relentless quest for miniaturization, increased performance, and efficiency. However, Moore’s Law is no longer a given and silicon is facing functional limitations as technology scales. To address these challenges and conti... » read more

Taking Data Center Serviceability To The Next Level
By Nozar Nozarian - 10 Sep, 2024 - Comments: 0

It is no secret that Artificial Intelligence (AI) workloads are driving an exponential growth in the scale of supercomputers and data centers. Training the latest LLM (Large Language Model), for instance, typically requires thousands of specialized processing cores running at full speed. As these models get more advanced with each generation, they need additional compute performance to absorb a... » read more

Are You Ready For HBM4? A Silicon Lifecycle Management (SLM) Perspective
By Faisal Goriawalla - 06 Aug, 2024 - Comments: 0

Many factors are driving system-on-chip (SoC) developers to adopt multi-die technology, in which multiple dies are stacked in a three-dimensional (3D) configuration. Multi-die systems may make power and thermal issues more complex, and they have required major innovations in electronic design automation (EDA) implementation and test tools. These challenges are more than offset by the advantages... » read more

Reducing Design Margins With Silicon Model Calibration
By Guy Cortez - 09 Jul, 2024 - Comments: 0

By Guy Cortez and Mark Laird It’s no secret to anyone that chip design gets harder every year. There are two major trends driving these ever-increasing challenges. The first is the continual scaling down to smaller design nodes. Although the pace of new node introduction has slowed somewhat in recent years, the impact of each new geometry and process is more dramatic than ever before. Acce... » read more

Automotive Electronics Reliability Requires In-Field Silicon Monitoring
By Lorin Kennedy - 11 Jun, 2024 - Comments: 1

By Lorin Kennedy and Dan Alexandrescu For everyday consumers, no products require reliability more than automobiles. While consumers may be willing accept their laptops and phones limiting performance or abruptly turning off when systems reach unacceptable temperature levels, that is not the case for the reliability of Advanced Driver-Assistance Systems (ADAS) or other safety critical system... » read more

Supporting Multiple Time Domains In SoC Production Test
By Hari Mani - 14 May, 2024 - Comments: 0

Complex system-on-chip (SoC) devices make every stage of the development flow harder, and the challenges continue even after the silicon is fabricated. Automatic test equipment (ATE) screening for defective wafers and assembled chips is always challenging. Production test engineers constantly struggle to minimize expensive test pattern memory, test each wafer or chip as quickly as possible, and... » read more

Reimagining PVT Monitoring IP For Advanced Node GAA Process
By Rohan Bhatnagar - 09 Apr, 2024 - Comments: 0

As process technology continues to evolve, so must design tools and the IP that support them. One example of an industry evolution is on the PVT monitoring IP side. The process, voltage, and temperature (PVT) monitors embedded within chips provide feedback on silicon status at every stage of the lifecycle, including mission use in the field. The data gathered from the monitors enables benefits ... » read more

Silent Data Corruption Considerations For Advanced Node Designs
By Jyotika Athavale - 12 Mar, 2024 - Comments: 0

Ensuring reliability, availability, and serviceability (RAS) has long been an important consideration for many types of electronic systems, with major implications for chip design. Clearly, military hardware must be very reliable, and servers and automotive systems are also expected to be available constantly. Some amount of failure is inevitable, so being able to repair, avoid, or mitigate fau... » read more

AI-Driven Test Optimization Solves Semiconductor Test Costs And Design Schedules
By Sri Ganta - 08 Feb, 2024 - Comments: 0

Artificial Intelligence has become a pervasive technology that is being applied to solve today’s complex problems, especially in the areas involving exponentially large amounts of data, their analysis, and corresponding decision making that are otherwise limited by human abilities. Therefore, complex challenges in semiconductor design, test and manufacturing are a perfect match for AI. The... » read more

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