Completing The Silicon Lifecycle Management Puzzle


The year 2020 will be remembered for many reasons. The global pandemic, the political struggles and the extreme weather will occupy our thoughts for many years. There was another event that occurred in 2020 that will also be remembered in a smaller, but very important portion of the world. It’s the year that Synopsys acquired Moortec to complete the silicon lifecycle management (SLM) puzzle. ... » read more

Making IC Test Faster And More Accessible: Part 2


Recently, my colleague Robert Ruiz described a new approach to scan test that utilizes the high-speed I/O (HSIO) ports that exist on most chips. The benefits of this new approach include reduced test time and cost thanks to the high-speed interface. Simplified pin electronics and tester setup are also benefits, as is the ability to run manufacturing tests in the field in support of silicon life... » read more

Making IC Test Faster And More Accessible: Part 1


The fundamental challenges of IC test have been the same for a long time. At the heart of all test strategies is controllability and observability. First, control the state of the chip with known test vectors and then observe the chip to determine if it exhibits good or faulty behavior. There have been many innovations over the years to make the required testing of chips more tractable. Thanks ... » read more

From Design To Deployment: How Silicon Lifecycle Management Optimizes The Entire IC Life Span


The beginning of the IC journey gets most of the attention in the semiconductor world – the challenges of design, test and manufacturing. But the reality is the entire lifecycle of a chip needs attention, requiring ways to ensure a chip’s intended and ongoing operation, especially in ever-changing operating environments where chips ultimately reside. The growing complexity of today’s e... » read more

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