ResNet-50 Does Not Predict Inference Throughput For MegaPixel Neural Network Models


Customers are considering applications for AI inference and want to evaluate multiple inference accelerators. As we discussed last month, TOPS do NOT correlate with inference throughput and you should use real neural network models to benchmark accelerators. So is ResNet-50 a good benchmark for evaluating relative performance of inference accelerators? If your application is going to p... » read more

Model Variation And Its Impact On Cell Characterization


EDA (Electronic Design Automation) cell characterization tools have been used extensively to generate models for timing, power and noise at a rapidly growing number of process corners. Today, model variation has become a critical component of cell characterization. Variation can impact circuit timing due to process, voltage, and temperature changes and can lead to timing violations, resulting i... » read more

How End-To-End Solutions Support Tomorrow’s Automotive Electrical Systems


We are living in a time of significant change and disruption in the automotive industry. The amount of electrical and electronic content in today’s vehicles continues to explode as consumers demand greater personalization of products and regular feature updates, and as tomorrow’s technologies such as autonomous and electric drive continue to develop. Meanwhile, established carmakers are gra... » read more

Electronics In Agriculture


In my post Jobs: Farmer I wrote about my experience as a teenager working on the farm owned (actually rented from the Duke of Badminton) by the father of one of my school friends. Electronics were nowhere to be found in those days. I recently watched some YouTube videos that show just how hi-tech farming has become now that Moore's Law has made accessible electronics that would have seemed ma... » read more

Dependent Failure Analysis For Safety-Critical IP And SoCs


By Shivakumar Chonnad, Radu Iacob, and Vladimir Litovtchenko Due to the increased complexity in safety-critical system hardware, software, and mechatronics, the functional safety development process must address systematic and random hardware failures. Numerous safety-related activities are performed during safety-critical IP and SoC developments, as part of the safety lifecycle, from produc... » read more

Protecting Chiplet Architectures With Hardware Security


Chiplets are gaining significant traction as they provide compelling benefits for advancing semiconductor performance, costs, and time to market. With Moore’s Law slowing, building more powerful chips translates into building bigger chips. But with chip dimensions pushing up against reticle limits, growing the size of chips is increasingly impractical. Chiplets offer a new path forward by dis... » read more

Chips Listening To Gibberish


We all talk gibberish once in a while. At least, I do. I might be in a silly mood, thinking aloud, listening to music or talking over the phone using my headphones (they are quite small, and if you don’t notice them, you could think I am crazy). Regardless of the circumstances, I mean no harm, I promise. However, it’s still possible that a passer-by could get distracted trying to figure out... » read more

Secure Silicon Lifecycle Management Architecture For Functional Safety


The rapid growth of electronics for automotive applications fueled by advanced ADAS systems pose new challenges for complex SoC design and Silicon Lifecycle Management (SLM) in the supply chain as well as in-field monitoring and management of the population of chips. In these modern complex devices, ensuring the correct and safe operation requires not only functional safety to check for reli... » read more

AI Design In Korea


Like many in the semiconductor design businesses, Arteris IP is actively working with the Korean chip companies. This shouldn’t be a surprise. If a company is building an SoC of any reasonable size, it needs network-on-chip (NoC) interconnect for optimal QoS (bandwidth and latency regulation and system-level arbitration) and low routing congestion, even in application-centric designs such as ... » read more

One More Time: TOPS Do Not Predict Inference Throughput


Many times you’ll hear vendors talking about how many TOPS their chip has and imply that more TOPS means better inference performance. If you use TOPS to pick your AI inference chip, you will likely not be happy with what you get. Recently, Vivienne Sze, a professor at MIT, gave an excellent talk entitled “How to Evaluate Efficient Deep Neural Network Approaches.” Slides are also av... » read more

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