Avoiding A $7.7B Chip Design Cost


For years, the story about semiconductor development cost and about EDA contributions has been pretty simple. Cost has been, is, and will likely be for a while, the single biggest issue in scaling development for more complex designs. The next big leap for verification productivity will be the close integration of verification and design engines, both vertically and horizontally as I have writt... » read more

Does Hardware/Software Verification Have To Be Broad And Deep? Check Out DVCon 2017


DVCon 2017 is upon us next week and even though it is called the “Design and Verification” conference, it is rising more and more to the system level. One of the aspects of interest is how verification seems to simultaneously become broader—covering more aspects to verify like software, power and performance—while also becoming more deep when it comes to application domains and their sp... » read more

Not All Software Is Like Elvis


January is traditionally my look-back and outlook month. Five years ago my year-end wish had been a census of software developers, and it is fascinating how software in the context of verification has evolved since then (more on this below). Also, most years I go into my garage, dust off my collection of IEEE Spectrum print editions from January five, ten and 15 years back to assess which of th... » read more

Top 7 Verification Trends For 2017—Changes In The Game Of Ecosystems


As the year 2016 comes to a close, how did my predictions from last year hold up to reality? They were all about horizontal and vertical integration. Spoiler alert—they almost all have moved closer to reality. Going forward into 2017, some of the trends will intensify, but the most interesting trend to watch will be how the game of ecosystems in the areas of mobile, server, and intelligent sy... » read more

What “Hamilton – An American Musical” Tickets And Emulation Have In Common


During a recent trip to New York, I managed to see “Hamilton, An American Musical”—despite the running joke about how hard it is to get tickets. The sale of “Hamilton” tickets teaches an interesting lesson about what I would call an “automatic feedback loop of value adjustment”. And believe it or not, it bears some resemblance to how verification users actually choose what engine ... » read more

“Eating Your Own Dog Food” When Developing An Emulator


It’s a great week for emulation week with ARM TechCon happening in Silicon Valley. Palladium Z1 is a finalist for Best Product in the categories “Best Chip” and “Best System” and we started the week with an announcement that Fujitsu adopted the Cadence Palladium Z1 Enterprise Emulation Platform for their ARMv8-based “Post-K Supercomputer Development.” Cadence has faced some of the... » read more

TSMC OIP, Vertical Integration And The Power of Ecosystems


After several attempts I’ve made it – my presentation at the TSMC OIP Ecosystem Forum was accepted this year. You may ask, what does a front-end guy like me do at a technology implementation forum like TSMC OIP? And why is he excited about it? The short answer is that it brings back my past. I am excited about how the front-end flows and implementation flows get connected in a closer way. I... » read more

How the Internet of Things Drives More Diverse Design Considerations


Last week I was in Taiwan, presenting at and attending CDNLive. It is always great to see the local progress. MediaTek presented on their adoption of Perspec System Verifier, highlighting how they increased throughput of test generation from 1 to 100 test cases per hour. Realtek reported on their use of JasperGold technology, as well as on their Palladium adoption, achieving between 30x to 50x ... » read more

Models Are Dead? Long Live Models


During the first half of this year I had more discussions with customers on models again. Are models back? For what purpose? In short, it looks like models are well adopted and in use for software development. For performance and architecture analysis, however, as a recent presentation from Renesas at CDNLive Japan shows, users just use RTL as that accuracy is required. In combination with emul... » read more

Balancing Emulation And FPGA-Based Prototyping For Software Development


This year’s Design Automation Conference (DAC) has just finished and confirmed some of the trends I discussed in my last blog, “The Top Five Trends in Verification to Watch For at DAC 2016”, specifically when it comes to the set of connected engines, or “COVE” as Jim Hogan dubbed it. The Cadence Theater at DAC is always a good opportunity to listen to hands-on customer experiences, an... » read more

← Older posts Newer posts →