DAC 2017: A Glimpse Of How The Future Is Enabled

Checking out two verification setups that incorporate emulation.


Last week’s Design Automation Conference in Austin gave great examples on how the future is enabled with next generation tools today. My favorite portions were Uhnder’s overview on “Agile Emulation” in the cloud, SirusXM’s presentation on how they used our portfolio of emulation and FPGA-based prototyping, the panel on “Smarter Verification” that I had organized and – of course – the keynote that was given by EDA legend Jose Costello, talking about the Internet of Things, as he is now CEO of Enlighted.

This was my 20th DAC, with 19 consecutive DACs since 1998. Even though they didn’t let me bring in popcorn, Joe Costello’s keynote gave me a movie-premiere excited feeling. I saw him give his “negative target fixation” speech back in 1997 in Munich, and after captivating 90 minutes without any slides, I decided that I wanted to leave actual chip design behind and join Cadence. Joe didn’t disappoint. His full keynote, called “IoT – Tales From The Frontline,” is posted here. In addition to his insights on what it takes to be successful in the IoT, I found his thoughts on timing most interesting. He actually killed a company with IoT products back in 2004 after four years because the ecosystem—in this case, the networks and the smartphone—was not ready to support it. Fascinating how important timing is.

Uhnder showed how they are enabling the future with tools that would have been dismissed as too futuristic just a couple of years ago. Their LinkedIn page describes them as “developing disruptive products for sensing, cognition, and communication for the Internet of Things (IoT) market.” In terms of target markets, they are “targeting the Industrial and Commercial IoT market, the Automatic Driver Assistance Systems (ADAS) market, the Augmented Reality and Virtual Reality market, the Unmanned Aerial Vehicles (Drones) market, the Personal Robotics market, the Industrial Proximity Sensor market and the Lighting market.”

Raghu Rao described Uhnder’s System-on-Chip development challenges for what he referred to as “software-defined systems” in his presentation “Agile Emulation for Software Development and SOC Verification.” These systems include board support packages (including multi-core OS environment and IO drivers), optimized application engines (including pipeline drivers and post-processing libraries), and a diagnostic multi-core framework with test programs. The key challenges (ever-growing complexity, high degrees of required flexibility requiring the full software stack prior to tape-out, and tight schedules with critical cross-discipline dependencies) make it impossible to keep the design flow as a sequential one.

Uhnder chose a combination of simulation and emulation for their dynamic verification needs. Palladium emulation was chosen because of its debug capabilities, its fast enough speed to run the full software stack in the MHz range for boot, diagnostic and application tests. Palladium build times were fast enough to enable frequent RTL updates and the I/O was enabled via transactors and models interface to host devices. The slide also read that the “Palladium Cloud interface is versatile and flexible.” While Cadence (Quickturn) had what was called QuickCycles since 2001, users simply consider remote access to emulation to be “cloud” and set up environments like the one in the picture, which allows developer platforms to stay the same from simulation though emulation to the actual chip.

Uhnder’s verification set-up in the cloud

While Uhnder is a great example of enabling the future of IoT with new approaches (like emulation in the cloud), another example came from SiriusXM in their presentation at the Cadence DAC Theatre, entitled “Full System Emulation and FPGA Prototyping Assures First Silicon Success.” Paul Krayeski, Vice President of IC Development at SiriusXM described how they used a portfolio of tools—Palladium emulation and Protium FPGA-based prototyping—to verify their baseband designs.

SiriusXM has worked on eight generations of baseband devices, from 240nm to 40nm. With first-pass success in every generation, I had to chuckle when Paul described the “Executive Stop Watch Test,” in which the team is measured by the time from first power on to live broadcast music through the device. His key question was how to maintain the track record of staying within the historical worst case of 3:57.47 (!), despite increasing design complexity.

SiriusXM’s software development setup using Protium

At the heart of their verification methodology is a synthesizable IQ Player that applies up to 30 seconds of real-time IQ signal from the RF to the baseband design, combined with external IP injection for longer sequences. SiriusXM always compares speed to the real-time processing. The baseline is a simulation that is 200,000X slower than real time. Palladium emulation is 600X slower than real time and allows 90 seconds of real-time IQ data to be processed in 15 hours—about 330X faster than in simulation. Emulation is used for full end-to-end data path processing, software validation of output services, live signal injection with service output validation and deterministic error injection to validate correct behavior.

The Protium set-up (shown above) runs another 5X faster, at 120X slower than real-time. It is focused on external IQ injection for IP samples. It also allows full end-to-end data path processing, supports two full systems and is used for software development. Specifically, SiriusXM does audio decoder library porting, operating system porting, ROM validation testing, application software development, and software testing with actual Flash, eMMC NAND, and EEPROM devices.

Given that visibility is more limited in FPGA, issues identified are re-created on Palladium with wave collection for debugging. SiriusXM could identify pre-silicon two AXI interface issues related to the multi-port DDR3 controller that was not identified on a Xilinx FPGA platform, which used a hardened controller/PHY, as well as incorrect endian format issues and reversed register controls. The bottom line is that the portfolio of emulation and FPGA-based prototyping was the winning combination, reduced time to bring-up, bring-up time itself was reduced, and even first silicon operational failure was prevented, which would have forced a silicon re-spin.

As I am running out of words for this blog, I will update on the “Smarter Verification” panel that was moderated by Ann Mutschler next time. Cadence’s Meera Collier did an initial write-up here.

It is amazing to see how EDA enables the future of our day-to-day lives, and how our tools get more and more advanced every year.

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