Dissolving The Barriers In Multi-Substrate 3D-IC Assembly Design


Advanced packaging continues to promise improved form factor, cost, performance, and functionality compared to the traditional transistor scaling on SoCs. This is done by integrating multiple dies on top of a substrate (organic or silicon). Besides multiple dies, multiple substrates can typically exist in a 3D-IC assembly. In this case, the benefits of advanced packaging are taken to a whole ne... » read more

Are Sustainability And Safety Gen Z’s Top Requirements In 2031?


This blog is my 125th on the "Frankly Speaking" channel on SemiEngineering. A big thanks to Ed and his team for a great run and for putting up with my musings! I had started work-related blogging back in 2008, more company-specific, and some of these have since then vanished from the internet. Who would have thought! For this anniversary, I am looking forward ten years to 2031 and how generatio... » read more

Intelligent Waveform Replay For Efficient Debug


There is no doubt that design reuse is essential for today’s massive system on chip (SoC) projects. No team, no matter how large or how talented, can design billions of gates from scratch for each new chip. From the earliest days, development teams have leveraged existing gate level designs and register transfer level (RTL) code whenever possible. The emergence of the commercial intellectual ... » read more

How To Extend The ‘Unscalable’ RISC Architectures


A couple of years ago, Erik McClure (a Microsoft software developer, at the time) published a blog entitled RISC Is Fundamentally Unscalable.  This blog was really quite interesting and made some very good points about the limitations of a pure RISC design. The limitations of a pure RISC design It takes me back: some of my first marketing tasks were around the religious war between RISC ... » read more

Verification Signoff Beyond Coverage


A common design view of verification signoff is to start with a comprehensive verification plan, covering every requirement defined among specifications and use-cases, the architectural definition, and any other relevant documents. Tests are then developed to cover every feature of the verification plan. Those tests are run and debugged, and identified issues are addressed within the design. Th... » read more

Three Technologies Enabling The Next Decade Of Hyperconnectivity


As it has become a tradition in my 15 years of blogging, January is a month of both reflection and outlook. At the beginning of 2022, I am excited that key themes from 5 and 10 years ago—3D integration, artificial intelligence and machine learning (AI/ML), and ubiquitous needs for more connectivity driving 4G and 5G networks—clearly have exceeded expectations and forecasts from that time. L... » read more

Using Symbolic Simulation For SRAM Redundancy Repair Verification


Innovations in Very Deep Sub-Micron technologies, such as the advent of three-dimensional FinFET transistor structures, have facilitated the implementation of very large embedded SRAM memories in System-on-Chip (SoC) designs to the point where they occupy the majority of the chip die area. To get maximum memory capacity on the smallest die area, SRAM bitcells are designed with the minimum possi... » read more

Dependable Verification Is The Foundation ICs Require


As our world becomes increasingly high-tech, it is easy to lose sight of the little things that make all of our fancy gadgets achieve optimal performance. The one thread that enables you to get all of the benefits of a new laptop, tablet, smartphone, or your automobile’s digital dashboard and connects the components that ensure best performance is the integrated circuit (IC). For as breath... » read more

Traceability, Unfamiliar But Critical


Many understand that traceability is a popular concept. Still, understanding traceability in detail is more challenging, especially in how it connects to familiar objectives in the semiconductor design space. A simple way to understand is this: When a customer (call them C) asks a semiconductor supplier (call them S) to build a device to meet a system objective, they provide S with specificatio... » read more

The Third Generation Of FPGA Prototyping


Bench setups with physical prototypes lie at the very heart of electrical and electronic engineering. With all due respect to the many powerful forms of modeling and simulation, at some point the engineering team wants to work with hardware. When a system is built entirely from existing components, it is possible to build a prototype of the product as soon as it has been designed. When the desi... » read more

← Older posts Newer posts →