AI Infrastructure At A Crossroads


By Ramin Farjadrad and Syrus Ziai There is a big push to achieve greater scale, performance and sustainability to fuel the AI revolution. More speed, more memory bandwidth, less power — these are the holy grails. Naturally, the one-two punch of StarGate and DeepSeek last week has raised many questions in our ecosystem and with our various stakeholders. Can DeepSeek be real? And if so, w... » read more

Fast Monte Carlo Simulations For Timing Variation Analysis


Process variations and device mismatches profoundly affect the latest ultra-small geometrical processes. Complexity creates additional factors that impact device manufacturing variability, which in turn impact overall yield. Monte Carlo (MC) simulations use repeated random sampling to relate process variations to circuit performance and functionality, thus determining how they impact yield. How... » read more

What IoMT Really Stands For


The basic goals of engineering include the achievement of a product’s purpose, safety, cost, manufacturability, and supportability, among other things. For internet of things (IoT) applications, much of the essential purpose relates to wireless communications that untether communication from wires and cables. This is especially true of the rapidly growing internet of medical things (IoMT), wh... » read more

Introduction Of High Bandwidth Embedded USB2v2 (eUSB2v2) Standard


Universal Serial Bus (USB) technology is the most popular connector in every computing device, but when it comes to embedded applications, where only a specific device function may be required, the architectural philosophy of the USB technology becomes inefficient. One example could be USB cameras. With increasing user expectations of camera resolution and frame rates, the bandwidth constrai... » read more

Redefining XPU Memory For AI Data Centers Through Custom HBM4: Part 3


This is the third and final of a series from Alphawave Semi on HBM4 and gives and examines custom HBM implementations. Click here for part 1, which gives an overview of the HBM standard, and here for part 2, on HBM implementation challenges. This follows on from our second blog, where we discussed the substantial improvements high bandwidth memory (HBM) provides over traditional memory tec... » read more

Why Circuit Designers And Test Engineers Need Impedance Analyzers


All engineers know resistance is usually bad news. It generates heat. It reduces efficiency. It wears out components and cuts operational lifetimes. However, resistance is not the only kind of opposition to the current. When more complex waveforms are involved (like in radio applications), the inductors and capacitors contribute a different kind of opposition that is highly dynamic and compl... » read more

Enhancing Power Reliability Through Design-Stage Layout Optimization


As integrated circuit (IC) designs continue to scale, the demand for efficient power management, performance optimization and reliable physical layout modification grows more critical. Meeting these power, performance and area (PPA) targets is essential for ensuring that IC designs operate effectively at advanced process nodes. One of the main challenges for design and verification engineers is... » read more

2024 Set The Stage For NoC Interconnect Innovations In SoC Design


What a year it’s been for Arteris! Reflecting on 2024, the company achieved exciting milestones and breakthroughs that pushed the boundaries of system-on-chip (SoC) design. A game-changing new technology was unveiled, a major product was launched, and existing solutions were tailored for AI, automotive, high-performance computing (HPC) and more. Along the way, we welcomed new partners and ... » read more

Achieving Successful Multi-Die Signoff


Multi-die designs leveraging 2.5D and 3D technologies are becoming crucial for various electronics applications, including high-performance computing (HPC), artificial intelligence (AI), automotive, and mobile devices. These designs allow the integration of dies from different foundries and technology nodes, enhancing density and interconnect speeds beyond traditional discrete dies. However, th... » read more

Redefining XPU Memory For AI Data Centers Through Custom HBM4: Part 2


This is the second in a three-part series from Alphawave Semi on HBM4 and gives insights into HBM implementation challenges. Click here for part 1, for an overview on HBM, and in part 3, we will introduce details of a custom HBM implementation. Implementing a 2.5D System-in-Package (SiP) with High Bandwidth Memory (HBM) is a complex process that spans across architecture definition, designi... » read more

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