Balancing Memory And Coherence: Navigating Modern Chip Architectures


In the intricate world of modern chip architectures, the "memory wall" – the limitations posed by external DRAM accesses on performance and power consumption growing slower than the ability to compute data – has emerged as a pivotal challenge. Architects must strike a delicate balance between leveraging local data reuse and managing external memory accesses. While caches are critical for op... » read more

Shedding More Light On Photonics For Multi-Die Systems


By Kenneth Larsen and Twan Korthorst Photonics harness the speed of light for fast, low-power, high-capacity data transfer. A tremendous amount of data needs to be moved swiftly across different components in a multi-die system. Considering this, exploiting the advantages of light is one way to mitigate heat dissipation and energy consumption concerns while delivering fast data transmission.... » read more

Extending DTCO For Today’s Competitive IC Landscape


As semiconductor components continue to shrink, the challenges associated with design-for-manufacturing (DFM) and design-technology co-optimization (DTCO) increase. The complexity of the IC design and manufacturing process demands an extension of traditional DFM and DTCO techniques to overcome the systematic failures tied to complex design-process interactions. Designers need to accelerate d... » read more

Unraveling PCIe 6.0 Loopback And Digital Near-End Loopback Feature


The PCIe specification has given a specific Link Training and Status State Machine (LTSSM) state named Loopback, which is intended for test and fault isolation use. Basically, it gives a mechanism that involves looping back the data that was received in the Loopback LTSSM state. The entry and exit behavior are specified, and all other details are implementation-specific. Loopback can op... » read more

Shattered Silos: 2024’s Top Technology Trends


Technological innovation is increasingly focused on solving pressing, global challenges like climate change, disaster response, and accessible, preventative healthcare. Time is of the essence in finding solutions to these issues. On the global stage, the deadline for the United Nations (UN) 2030 Agenda for Sustainable Development, a framework of strategies to tackle climate change, improve heal... » read more

The Good Old Days Of EDA


Nostalgia is wonderful, but there is something about being involved in the formative years of an industry. Few people ever get to experience it, and it was probably one of the most fortuitous events to have happened in my life. Back in the early '80s, little in the way of design automation existed. There were a few gate- and transistor-level simulators, primarily for test and a few 'calculators... » read more

Nascent Chiplet Tech Gaining Attention In Defense and Commercial Industries


The economic benefits derived from Moore's Law have changed, and not for the better. This shift – especially on the manufacturing side of system-on-chip (SoC) devices, has both the defense and commercial customers in the semiconductor industry wondering what will come next. One way to extend Moore's Law's cost, feature, and size benefits is with multi-chip technology, now commonly known as... » read more

Considerations For Accelerating On-Device Stable Diffusion Models


One of the more powerful – and visually stunning – advances in generative AI has been the development of Stable Diffusion models. These models are used for image generation, image denoising, inpainting (reconstructing missing regions in an image), outpainting (generating new pixels that seamlessly extend an image's existing bounds), and bit diffusion. Stable Diffusion uses a type of dif... » read more

Help, 3D-IC Is Stuck In A Country Song


Every time I focus on three-dimensional (3D) integrated circuit (IC) design, I start hearing the Luke Bryan song “Rain Makes Corn, Corn Makes Whiskey.” Not because I need a strong drink to work with 3D-IC designs, but because there is a similar, although slightly more complicated, series of cause and effect issues that impact 3D-ICs. Pushing electrons through very thin metal wires and switc... » read more

A Path To Increase Cell Utilization Rate And Decrease Routing Congestion In Chip Design Floorplanning


What do chip floorplanning and city planning have in common? As it turns out, quite a lot. This was the premise for an award-winning talk given by MediaTek at this year’s Synopsys User Group (SNUG) in Taiwan. Urban city development was used as an example to understand how utilization rate (UR) and congestion relate to chip planning. UR was defined in the example as population density while... » read more

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