category: Blogs – SLD

category: IoT, Security & Automotive

Timing Library LVF Validation For Production Design Flows
By WeiLii Tan - 27 Feb, 2020 - Comments: 3

Variation modeling has evolved over the past several years from a single derating factor that represents on-chip variation (OCV), to Liberty Variation Format (LVF), today’s leading standard format that encapsulates variation information in timing libraries (.libs). LVF data is considered a requirement for advanced process nodes 22nm and below. At the smallest process nodes such as 7nm and ... » read more

Keep The Wooden Horse Out Of Your Chip
By Sergio Marchese - 27 Feb, 2020 - Comments: 0

The OneSpin's Holiday Puzzle tradition has reached its fourth year: hear, hear! In December 2016, OneSpin challenged engineers to solve the Einstein riddle using assertions and a formal verification tool. In December 2017, the challenge was to model the hardest Sudoku in the world using assertions and find a solution with a formal tool. The OneSpin 2018-19 Holiday Puzzle asked engineers to desi... » read more

Simulation: Go Parallel Or Go Home
By Taruna Reddy - 27 Feb, 2020 - Comments: 0

Although complemented by other valuable technologies, functional simulation remains at the heart of semiconductor verification. Every chip project still develops a testbench, usually compliant with the Universal Verification Methodology (UVM), and a large test suite. Constrained-random stimulus generation has largely replaced hand-crafted tests, but at the expense of much more simulation time. ... » read more

Bluetooth LE Audio Makes Its Debut
By Shewan Yitayew - 27 Feb, 2020 - Comments: 0

The Bluetooth Low Energy 5.2 specification introduces LE audio, which is a significant step forward for Bluetooth audio, both in terms of sounds quality and functionality. LE Audio, based on our new iEB110 IP, will enable manufacturers to create low power audio devices that offer several revolutionary new features that weren’t possible before, even with third-party proprietary solutions. T... » read more

SoC Co-Emulation Using Zynq Boards
By Michelle Mata - 27 Feb, 2020 - Comments: 0

Have you ever worked on a group project where you had to combine your work with that of a colleague of a different engineering discipline but the absence of an efficient means of doing so affected the project’s overall outcome? Well, for software and hardware engineers developing an SoC, the merging of their respective engineering efforts for verification purposes is a big challenge. Early... » read more

Balancing Flexibility And Quality In SRAM Verification
By Elven Huang - 30 Jan, 2020 - Comments: 0

Memory is an essential component of system-on-chip (SOC) designs, especially at advanced nodes. SoCs use a variety of memory block types, such as static random-access memory (SRAM) and dynamic RAM (DRAM), to perform computations. The SRAM blocks, which consist of an assembly of specialized calls that abut or overlap one another in a specific arrangement that complies with the circuit specificat... » read more

New Parasitic Extraction Requirements In Custom Design For The Next Wave Of SoCs
By Ash Patel - 30 Jan, 2020 - Comments: 0

Fast growing markets like 5G, biotechnology, AI, and automotive are driving the new wave in semiconductor design and the need for highly integrated system on chip (SoCs). Power management, sensors, RF and precision analog functionality are all integrated on the same substrate which poses new challenges for custom design tools. Specifically, there are new challenges for parasitic extraction that... » read more

Authentication In The IoT Age
By Marc Canel - 30 Jan, 2020 - Comments: 0

We all know passwords are a problem. We have too many of them to remember, but too many of them are reused to make them secure. No surprise that they are the root cause of the vast majority of data breaches. Fortunately, clever minds are working at ways to replace them and they have come together to create the FIDO (Fast IDentity Online) Alliance. The FIDO Alliance was created in 2013 to de... » read more

Verification Planning And Management With Formal
By Tom Anderson - 30 Jan, 2020 - Comments: 0

Over the last twenty years, formal verification has grown from a niche technology practiced only by specialists to an essential part of mainstream chip development. Along the way, several advances were needed to make wider adoption of formal feasible. These included the standardization of assertion languages, enhanced formal engine performance and capacity, better debug capabilities, and pushbu... » read more

2019 – The Year Of The “Dynamic Duo” Of Emulation and Prototyping
By Frank Schirrmeister - 30 Jan, 2020 - Comments: 0

In technology, we are always trying to figure out when we have reached critical mass, have crossed the chasm, or even can be considered mainstream. We all have seen the adoption curves for consumer products. In design and verification technology, a distinct B2B setting with fewer end customers than in the B2C domain, the situation seems to be even worse as there is no “one flow” to design a... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2025 SMG   |  Terms of Service  |  Privacy Policy