Successful Design Of Power Management Chips


With an industry as large as semiconductors, there are often surprises lurking in some of the more specialized product categories. Everyone knows that huge chips such as CPUs and GPUs command high prices and that memory chips are ubiquitous. However, the domain of power management integrated circuits (PMICs) is less well known to many observers. PMICs are impressive in terms of their technol... » read more

The Latest Wireless Industry Use Cases


The wireless industry evolves constantly; GSMA estimates that mobile technologies and services generated 5% of the global GDP in 2022, which equates to $5.2 trillion of economic value. In parallel, more than 5.4 billion people subscribed to a mobile service, with 4.4 billion connected to the mobile internet. These numbers are impressive, but there is much more to come. 5G networks promise exp... » read more

Outlook 2025: Embracing Chiplets


The semiconductor industry is rapidly evolving, and as we look towards 2025, chiplets are at the forefront of this transformation. The shift from traditional monolithic system-on-chip (SoC) designs to chiplet-based architectures is gaining momentum, driven by the need to meet ever-increasing computing demands. This evolution is not just a trend; it represents a fundamental change in how we appr... » read more

Managing Reflections With Terminations


Have you heard recommendations to use a particular termination in particular situations for good signal integrity? Have you ever wondered how to incorporate terminations in your design? While there are typical use cases for various terminations, sometimes engineers use termination techniques based on a recommendation or assumption that may not work, or at least may not be optimal, for their par... » read more

Why 40G UCIe IP?


AI applications are bringing new challenges to the semiconductor industry. There is an increased demand for greater bandwidth, especially for compute and networking applications to support the high data processing required by deep learning and machine learning algorithms. The requirements for these AI applications are different for die-to-die interfaces. Let’s take 100Tb networking switches a... » read more

Reducing SoC Power With NoCs And Caches


Today’s system-on-chip (SoC) designs face significant challenges with respect to managing and minimizing power consumption while maintaining high performance and scalability. Network-on-chip (NoC) interconnects coupled with innovative cache memories can address these competing requirements. Traditional NoCs SoCs consist of IP blocks that need to be connected. Early SoCs used bus-based archi... » read more

Revolutionizing High-Performance Silicon With Next-Gen Chiplets


By Shivi Arora and Sue Hung Fung As 5G wireless communications systems continue to be deployed, enterprises are busy planning for 6G—the next generation of wireless communications set to transform our lives. Poised to merge communication and computing, 6G promises to create a hyperconnected world that blends digital and physical experiences with ultra-fast speeds and low latency as a start... » read more

Locking When Emulating Xtensa LX Multi-Core On A Xilinx FPGA


Today's high-performance computing systems often require the designer to instantiate multiple CPU or DSP cores in their subsystem. However, the performance gained by using multiple CPUs comes with additional programming complexity, especially when accessing shared memory data structures and hardware peripherals. CPU cores need to access shared data in an atomic fashion in a multi-core environme... » read more

Mastering Cyber Awareness: Training For The Digital Battlefield


In today’s digital battlefield, cyber awareness is crucial for warfighters. To effectively prepare them, it’s essential to create realistic and detailed models of mobile networks, encompassing both physical and virtual infrastructure. This is where network modeling software comes into play, offering a high-fidelity approach to enhance cyber situational awareness. A high-fidelity modeling an... » read more

UMI: Extending Chiplet Interconnect Standards To Deal With The Memory Wall


With the Open Compute Project (OCP) Summit upon us, it’s an appropriate time to talk about chiplet interconnect (in fact the 2024 OCP Summit has a whole day dedicated to the multi-die topic, on October 17). Of particular interest is the Bunch of Wires (BoW) interconnect specification that continues to evolve. At OCP there will be an update and working group looking at version 2.1 of BoW. (... » read more

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