category: Blogs – SLD

category: IoT, Security & Automotive

Inside UVM
By Vatsal Choksi - 26 Oct, 2017 - Comments: 0

We have all been witnesses to the rapid improvements of the iPhone processor chip every year. With the iPhone 8 featuring the newest A11 Bionic at 10 nm FinFET with 4.3 billion transistors, I can’t personally fathom the amount of the verification effort needed for this type of SoC - the required manpower and time to get the job done is absolutely mind-boggling. Thankfully, we have several pre... » read more

Look Ma, No Hands! Functional Safety From The Driver’s Seat
By McKenzie Ross - 26 Oct, 2017 - Comments: 0

Every so often, I undertake a project that reminds me why I love working in semiconductor marketing. Back in August, I hopped behind the wheel of a Tesla Model X to film a video for OneSpin about how formal verification can help designers to satisfy the ISO 26262 automotive safety standard. If you haven't yet seen the video, you can watch it here: http://bit.ly/2ycK5Yp The Model X itself was... » read more

Four Steps To Verifying An SSD Controller With Emulation
By Ben Whitehead - 26 Oct, 2017 - Comments: 0

By Ben Whitehead and Paul Morrison Datacenters, cloud computing, the IoT, and all things electronic demand that huge amounts of data and information are stored securely and accessible anywhere at any time. This requirement is driving the adoption of new storage technologies. The capacity, size and performance of solid state drives (SSDs) make it a very interesting technology. It offers h... » read more

Shhhhh… Deadlocks Anonymous In Session
By Rajesh Ramanujam - 26 Oct, 2017 - Comments: 0

I am sure there is an anonymous group – like Alcoholics Anonymous – headquartered in Silicon Valley, meeting every quarter to discuss the deadlocks that have paralyzed their products, roadmap and deployments. In discreet venues in every town, small groups of engineers huddle together to share war stories about the disgruntled customers whose trust was lost because of a deadlock discovered o... » read more

Continuous Integration
By Zach Lasiuk - 26 Oct, 2017 - Comments: 0

In this article, I tackle the classic question engineers developing software for custom integrated circuits (ICs) grapple with constantly: How do I test my software before the hardware team gets me a working silicon chip? No ‘one size fits all’ solution is provided here (look for that alongside my pet unicorn); instead I detail an easy-to-use yet powerful approach to solve this proble... » read more

Use Model Versatility: Key To Return On Investment For Emulation
By Frank Schirrmeister - 26 Oct, 2017 - Comments: 0

When we announced Palladium Z1 now almost two years ago in November 2015, we emphasized versatility of use models as a key component to optimize return on investment when adopting emulation. Today, our biggest customers are using emulation as a compute resource with 10s of projects in parallel, and they are running a large number of different use models on it. This year alone, more than 30 cust... » read more

Generically Reusable IP No One Uses
By Neil Johnson - 02 Oct, 2017 - Comments: 5

I can’t tell you how many times this line has jumped into my mind over the last couple decades, probably because I lost count sometime in 1998... Manager: “...why do they put a guarantee on the box then?” Tommy: “‘Cause they know all they sold you was a guaranteed piece of s***.” That’s an exchange from the movie Tommy Boy, a classic from my university days. Tommy Callaha... » read more

System Design And Verification Challenges: Are They On- Or Off-Chip?
By Frank Schirrmeister - 28 Sep, 2017 - Comments: 0

What are the next natural items for mobile devices to be integrated? From 2002 to today, previously separate items (like GPS, cameras and keyboards) have been integrated into the phone. They caused a frenzy of integration within systems on chips. Now we have the Internet of Things (IoT) adding a trillion devices to the picture. Which ones are to be integrated, if any? What does all this mean fo... » read more

Get To Know The Gate-Level Power Aware Simulation
By Progyna Khondkar - 28 Sep, 2017 - Comments: 1

The post-synthesis gate-level netlist (GL-netlist) based PA simulation input requirements are mostly the same as RTL simulation. However, the design under verification here is the GL-netlist from synthesis, so logic gates from standard, MV and Macro cell Liberty libraries are already inserted or instantiated in the design. Hence power aware simulation (PA-SIM) at post-synthesis also requires Li... » read more

Prototyping Building Blocks
By Tom De Schutter - 28 Sep, 2017 - Comments: 0

Lego has existed for 85 years. The company was founded August 10, 1932, and after all these years, the concept of building structures big and small still hasn’t lost any of its charm. For my children, now 10 and 12, it is probably the most played with toy throughout their childhood. As with any new purchase, they initially and carefully build the specific design for the instructions included ... » read more

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