category: Blogs – SLD

category: IoT, Security & Automotive

The CEO Outlook Returns
By Bob Smith - 23 Mar, 2017 - Comments: 0

One of the more popular events hosted by the EDA Consortium (EDAC, to those in the know) was the CEO Forecast held at the start of each year. It was phased out several years ago for a number of reasons, including logistics and scheduling. Attendance was never one of them. As I took the reins of EDAC two years ago, I repeatedly heard how much that evening was missed. Members and non-members h... » read more

AI Storm Brewing
By Ed Sperling - 23 Feb, 2017 - Comments: 0

AI is coming. Now what? The answer isn't clear, because after decades of research and development, AI is finally starting to become a force to reckon with. The proof is in the M&A activity underway right now. Big companies are willing to pay huge sums to get out in front of this shift. Here is a list of just some of the AI acquisitions announced or completed over the past few years: ... » read more

Could DVCon Be Better?
By Brian Bailey - 23 Feb, 2017 - Comments: 0

DVCon is undoubtedly the best conference in the industry if your interest is functional verification. In the past, it has also had a slant toward design. The focus is quite simply based on the standards activity going on within [getentity id="22028" e_name="Accellera"], the EDA industry's body that turns problems into solution in a short space of time. As those standards mature, they are handed... » read more

Better Code With RTL Linting And CDC Verification
By Sergei Zaychenko - 23 Feb, 2017 - Comments: 0

Automated design rule checking, or linting, has been around in RTL verification for at least a couple decades, yet still many HDL designers completely ignore this simple yet very powerful bug hunting method. Why would a busy designer need to run this annoying warning generator? The hostility against using conventional linting tools is often explained by the enormous amount of output noise, limi... » read more

IP Qualification During RTL Synthesis
By Sudhakar Jilla - 23 Feb, 2017 - Comments: 0

By Sudhakar Jilla and Arvind Narayanan The use of IP (intellectual property) as basic building blocks is an established practice for SoC designs. Most IP is developed without chip-level context and very little knowledge about physical design, which can introduce unwanted schedule risk into the design process. Much of the risk of IP development can be mitigated by using new physical synthesis... » read more

Software Modeling And KPI
By Pat Sheridan - 23 Feb, 2017 - Comments: 0

In Software Modeling Goes Mainstream, Ed Sperling recently wrote how chipmakers are applying use case modeling techniques to better understand the interactions between software and hardware and how they impact system performance and energy efficiency. As the software content for multicore SoCs grows, these interactions are becoming increasingly complex. For system designers and SoC architect... » read more

Advanced ASICs Are A Team Sport
By Mike Gianfagna - 23 Feb, 2017 - Comments: 0

The recent Super Bowl proved that a team with conviction and focus can do anything. This notion comes in handy when you think about the nearly impossible job of designing and manufacturing an advanced ASIC – in finFET technologies, with an interposer, multiple die, and never-before-proven throughput rates. For these kind of advanced technologies, it does take a village. What works is open, tr... » read more

Does Hardware/Software Verification Have To Be Broad And Deep? Check Out DVCon 2017
By Frank Schirrmeister - 23 Feb, 2017 - Comments: 0

DVCon 2017 is upon us next week and even though it is called the “Design and Verification” conference, it is rising more and more to the system level. One of the aspects of interest is how verification seems to simultaneously become broader—covering more aspects to verify like software, power and performance—while also becoming more deep when it comes to application domains and their sp... » read more

Find Your Way To San Jose Next Week… For DVCon, Of Course!
By Dave Kelf - 23 Feb, 2017 - Comments: 0

If you’re asked “Do you know the way to San Jose?” in the next few days, chances are it’s a newbie to DVCon. Everyone else in chip design verification knows the way to the annual Design and Verification Conference and Exhibition about to convene at the San Jose DoubleTree Hotel. This year’s program is stacking up to be an insightful and educational four days of tutorials, paper ses... » read more

Rush Hour On The Technology Roadmap
By Mike Gianfagna - 30 Jan, 2017 - Comments: 0

Starting this week, the International Solid State Circuits Conference (ISSCC) will commence at the Marriott in downtown San Francisco. This prestigious conference showcases the latest semiconductor innovations from around the world. Looking at the advance program, one can’t help but notice a shift in the work presented. The conference theme this year is: “Intelligent Chips for a Smart World... » read more

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