category: Low Power-High Performance

category: IoT, Security & Automotive

DDR5 PMICs Enable Smarter, Power-Efficient Memory Modules
By Tim Messegee - 16 May, 2024 - Comments: 0

Power management has received increasing focus in microelectronic systems as the need for greater power density, efficiency and precision have grown apace. One of the important ongoing trends in service of these needs has been the move to localizing power delivery. To optimize system power, it’s best to deliver as high a voltage as possible to the endpoint where the power is consumed. Then a... » read more

How Quickly Can You Take Your Idea To Chip Design?
By Kira Jones - 16 May, 2024 - Comments: 0

Gone are the days of expensive tapeouts only done by commercial companies. Thanks to Tiny Tapeout, students, hobbyists, and more can design a simple ASIC or PCB design and actually send it to a foundry for a small fraction of the usual cost. Learners from all walks of life can use the resources to learn how to design a chip, without signing an NDA or installing licenses, faster than ever before... » read more

Enabling Multiscale Simulation
By Adarsh Chaurasia - 16 May, 2024 - Comments: 0

As product development teams face increasingly complex challenges — including the need for greater sustainability — there’s a growing awareness of the critical contributions made by materials. Many of our most pressing engineering challenges, from renewable energy grids to green transportation, rely on identifying or creating the right materials. Historically, materials discovery, mate... » read more

MPAM-Style Cache Partitioning With ATP-Engine And gem5
By Hristo Belchev - 16 May, 2024 - Comments: 0

The Memory Partitioning and Monitoring (MPAM) Arm architecture supplement allows for memory resources (MPAM MSCs) to be partitioned using PARTID identifiers. This allows privileged software, like OSes and hypervisors to partition caches, memory controllers and interconnects on the hardware level. This allows for bandwidth and latency controls to be defined and enforced for memory requestors. ... » read more

Running More Efficient AI/ML Code With Neuromorphic Engines
By Karen Heyman - 16 May, 2024 - Comments: 0

Neuromorphic engineering is finally getting closer to market reality, propelled by the AI/ML-driven need for low-power, high-performance solutions. Whether current initiatives result in true neuromorphic devices, or whether devices will be inspired by neuromorphic concepts, remains to be seen. But academic and industry researchers continue to experiment in the hopes of achieving significant ... » read more

Power/Performance Costs In Chip Security
By Adam Kovac - 16 May, 2024 - Comments: 0

Hackers ranging from hobbyists to corporate spies and nation states are continually poking and prodding for weaknesses in data centers, cars, personal computers, and every other electronic device, resulting in a growing effort to build security into chips and electronic systems. The current estimate is that 60% of chips and systems have some type of security built in, and that percentage is ... » read more

Fallback Fails Spectacularly
By Steve Roddy - 16 May, 2024 - Comments: 0

Conventional AI/ML inference silicon designs employ a dedicated, hardwired matrix engine – typically called an “NPU” – paired with a legacy programmable processor – either a CPU, or DSP, or GPU. The common theory behind these two-core (or even three core) architectures is that most of the matrix-heavy machine learning workload runs on the dedicated accelerator for maximum efficienc... » read more

High-Level Synthesis Enables The Next Generation Of Edge AI Accelerators
By Siemens EDA - 15 May, 2024 - Comments: 0

AI is becoming pervasive. But the ever increasing complexity is a challenge for IoT systems. Achieving the highest levels of performance and efficiency in edge AI means going beyond software and off the shelf hardware. Bespoke hardware accelerators in FPGA or ASICs can deliver much higher performance while consuming less energy. Building these accelerators with High-Level Synthesis slashes desi... » read more

Three Ways To Speed Up Timing Closure Of High-Speed PCB Interfaces
By Cadence - 15 May, 2024 - Comments: 0

On advanced high-speed interfaces, timing closure can be an iterative process that can be time-consuming and frustrating. PCB designers need techniques and tools to make the process more efficient, so they can contribute to an overall faster time to market for the design. This article discusses three ways that the new Cadence Allegro TimingVision environment speeds up timing closure of high-spe... » read more

Innovating Electric Mobility: Simulation Solutions For Electric Machines
By Ansys - 15 May, 2024 - Comments: 0

Automakers desire solutions that can easily scale to new applications of next generation vehicles. Electrified propulsion technology is one main area where EV engineers are pushing the boundaries. Electric machine design and integration choices have system-level impacts that directly influence an automaker’s time to market and even overall market adoption. With Ansys multiphysics simulatio... » read more

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