category: Low Power-High Performance

category: Auto, Security & Edge AI

From Discovery To High-Speed Delivery: A Unified Verification Approach For UCIe 3.0 Features And Manageability
By Ujjwal Negi - 11 Sep, 2025 - Comments: 0

By Ujjwal Negi and Prashant Dixit The Universal Chiplet Interconnect Express (UCIe) standard is redefining multi-die integration, enabling high-performance, scalable connections between heterogeneous chiplets. UCIe 2.0 introduced a dedicated manageability layer — a control plane for configuring, monitoring, and coordinating chiplet management elements independently from mainband and sideba... » read more

Coloring Optical Signals For More Bandwidth In Data Centers
By Bryon Moyer - 11 Sep, 2025 - Comments: 1

Copper cabling has been the workhorse for moving data inside of AI and HPC data centers, but fiber is nipping at its heels. Optics brings three possible bandwidth multipliers — wavelength-division multiplexing (WDM), the use of different modes, and polarization. Each has a role in longer-distance optical links, but the tradeoffs are different in the data center. WDM appears poised to boost... » read more

Rethinking AI Infrastructure: The Rise Of PCIe Switches
By Vanessa Do - 11 Sep, 2025 - Comments: 0

When thinking of AI, images of futuristic robots or self-driving cars may come to mind. What might not come to mind are the unsung hardware component heroes that are quietly enabling such complex systems. Among these, PCI Express (PCIe) switches might seem to be a boring topic to write about, much less read. But here's the twist—they are nothing short of revolutionary when it comes to empower... » read more

The Demise Of Static Timing Verification?
By Brian Bailey - 11 Sep, 2025 - Comments: 0

The chip industry traditionally has relied on margins to help them mitigate timing problems, but an increasing array of factors are now influencing timing. Can static timing analysis evolve to address these problems? Static timing verification (STA) was a cornerstone technology for the acceptance of the register transfer level (RTL) abstraction. It showed that functionality would not be impa... » read more

How Neural Super Sampling Works: Architecture, Training, And Inference
By Liam O'Neil - 11 Sep, 2025 - Comments: 0

This blog post is the second in our Neural Super Sampling (NSS) series. The post explores why we introduced NSS and explains its architecture, training, and inference components. In August 2025, we announced Arm neural technology that will ship in Arm GPUs in 2026. The first use case of the technology is Neural Super Sampling (NSS). NSS is a next-generation, AI-powered upscaling solution. ... » read more

Modern Factories Thrive By Manufacturing Smarter With Simulation
By Jennifer Procario - 11 Sep, 2025 - Comments: 0

By Jennifer Procario and Peter Slättman Automation induces anxiety in those who fear that technology will replace humans in the workforce. But as we transition from Industry 4.0 to 5.0, some apprehension could be alleviated with a shift in focus. The fourth industrial revolution centered on technology, but the fifth emphasizes human interaction and collaboration with technology. The Europ... » read more

Report: The Road to Artificial General Intelligence: Achieving the Next Era of Intelligence
By Arm - 10 Sep, 2025 - Comments: 0

Explore how industry leaders are defining artificial general intelligence (AGI) and what it may take to reach it. Developed by MIT Technology Review and Arm, this deep dive examines accelerating timelines, the compute innovations shaping progress, and why today’s models still fall short of true intelligence. Designed for engineers, researchers, and technology leaders navigating the future of ... » read more

HBM4 Memory: Break Through to Greater Bandwidth
By Rambus - 10 Sep, 2025 - Comments: 0

Delivering unrivaled memory bandwidth in a compact, high-capacity footprint, has made HBM the memory of choice for AI training. HBM4 is the fourth major generation of the HBM standard, with new power management and RAS features. The Rambus HBM4 Controller provides industry-leading performance to 10.0 Gb/s, enabling a memory throughput of over 2.5 TB/s for training systems, generative AI and oth... » read more

The Feasibility Of Deploying FPGA-Based TCEP Synchronization In Real-World Quantum Networks
By Fraunhofer IIS/EAS - 10 Sep, 2025 - Comments: 0

Precise time synchronization is a key challenge in building distributed quantum systems – and it plays a crucial role in secure communications, quantum computing, sensing, the foundations of future 6G networks and the quantum internet. In the paper titled "TCEP-Based Synchronization for Practical Communication Network,"researchers from TU Dresden, IIT Dharwad, Fraunhofer Institute for Inte... » read more

Verifying The Evolving UCIe Landscape
By Siemens EDA - 10 Sep, 2025 - Comments: 0

This paper details a verification strategy for UCIe 3.0 designs, integrating both legacy manageability architecture and emerging UCIe 3.0 features into a reusable, scalable framework. Built on a layered UVM architecture, Questa One Avery VIP for UCIe enables flexible modeling of complex domains through configurable APIs and supports automated discovery and routing table setup for both direct an... » read more

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