category: Low Power-High Performance

category: IoT, Security & Automotive

The Seven Pillars Of IC Package Physical Design
By Keith Felton - 15 Feb, 2024 - Comments: 1

Today’s heterogeneously integrated semiconductor packages represent a breakthrough technology that enables dramatic increases in bandwidth and performance with reduced power and cost compared to what can be currently achieved in traditional monolithic SoC designs. Figure 1. A heterogeneously integrated device with 47 chiplets. (Image Source: Intel) The evolving landscape of packagin... » read more

Expecting The Unexpected: Analyzing A Data Center Cooling Failure
By Mark Seymour - 15 Feb, 2024 - Comments: 0

Data center thermal management is often a reactive process. Servers issue warning messages, monitoring alarms activate, or employees express concern about general temperature levels/hotspots and then management decides what to do next. For incremental issues, once known, the necessary steps can be taken to resolve or improve these issues; however, what happens when a potential thermal issue onl... » read more

Generative AI On Mobile Is Running On The Arm CPU
By Adnan Al-Sinan - 15 Feb, 2024 - Comments: 0

By Adnan Al-Sinan and Gian Marco Iodice 2023 was the year that showcased an impressive number of use cases powered by generative AI. This disruptive form of artificial intelligence (AI) technology is at the heart OpenAI's ChatGPT and Google’s Gemini AI model, with it demonstrating the opportunity to simplify work and advance education through generating text, images, or even audio content ... » read more

What Is A Chiplet, And Why Should You Care?
By Roberto Piacentini Filho - 15 Feb, 2024 - Comments: 0

Chiplets are a new way to build system-on-chips (SoCs) that can improve yields and reduce costs by more than 45%. It partitions the chip into discrete elements and connects them with a standardized interface, allowing designers to meet performance, efficiency, power, size, and cost challenges in the 5/6G, AI, and VR era. Unlike monolithic SoCs, chiplets enable an open ecosystem of modular co... » read more

Thanks For The Memories!
By Steve Roddy - 15 Feb, 2024 - Comments: 0

“I want to maximize the MAC count in my AI/ML accelerator block because the TOPs rating is what sells, but I need to cut back on memory to save cost,” said no successful chip designer, ever. Emphasis on “successful” in the above quote. It’s not a purely hypothetical quotation. We’ve heard it many times. Chip architects — or their marketing teams — try to squeeze as much brag-... » read more

Impact Of 3DHI On Aerospace And Government Applications
By Ian Land - 15 Feb, 2024 - Comments: 0

By Ian Land, Kenneth Larsen, and Rob Aitken With challenging size, weight, and power (SWaP) requirements, chip designs for aerospace, defense, and government applications are a unique breed. No surprise here, considering systems like satellites and submarines must operate reliably in the distinctly harsh environments of outer space and ocean depths, respectively. Given the SWaP criteria a... » read more

AI Tradeoffs At The Edge
By Ann Mutschler - 15 Feb, 2024 - Comments: 0

AI is impacting almost every application area imaginable, but increasingly it is moving from the data center to the edge, where larger amounts of data need to be processed much more quickly than in the past. This has set off a scramble for massive improvements in performance much closer to the source of data, but with a familiar set of caveats — it must use very little power, be affordable... » read more

Re-architecting Hardware For Energy
By Brian Bailey - 15 Feb, 2024 - Comments: 0

A lot of effort has gone into the power optimization of a system based on the RTL created, but that represents a small fraction of the possible power and energy that could be saved. The industry's desire to move to denser systems is being constrained by heat, so there is an increasing focus on re-architecting systems to reduce the energy consumed per useful function performed. Making signifi... » read more

SRAM Scaling Issues, And What Comes Next
By Karen Heyman - 15 Feb, 2024 - Comments: 0

The inability of SRAM to scale has challenged power and performance goals forcing the design ecosystem to come up with strategies that range from hardware innovations to re-thinking design layouts. At the same time, despite the age of its initial design and its current scaling limitations, SRAM has become the workhorse memory for AI. SRAM, and its slightly younger cousin DRAM, have always co... » read more

IC Package Physical Design Best Practices
By Siemens EDA - 15 Feb, 2024 - Comments: 0

Historically IC package design has been a relatively simple task which allowed the die bumps to be fanned out on a package substrate to a floorplan geometry suitable for connecting to a printed circuit board (PCB). But today the industry is moving to disaggregation of traditional monolithic SoC functions into chiplets often interfaced with local high-speed memory to avoid silicon reticle limits... » read more

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