What’s needed to design the latest heterogeneous designs using HBM and chiplets.
Historically IC package design has been a relatively simple task which allowed the die bumps to be fanned out on a package substrate to a floorplan geometry suitable for connecting to a printed circuit board (PCB). But today the industry is moving to disaggregation of traditional monolithic SoC functions into chiplets often interfaced with local high-speed memory to avoid silicon reticle limits and yield challenges. Today’s packages are now complex systems containing high-speed chiplet2chiplet interfaces such as UCIe and BoW along with HBM for the memory all heterogeneously integrated on a high-performance substrate.
In order to efficiently design new types of IC packages, designers and design teams need to embrace a new emerging set of best practice design techniques, processes and methodologies that are covered in this eBook:
To read more, click here.
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