The Computational Electromagnetics Simulation Challenge Of 3D-IC


By Kelly Damalou and Matt Commens Innovation in semiconductor design today is energized primarily by AI/ML, data centers, autonomous and electric vehicles, 5G/6G, and IoT. Recently developed 2.5 and 3D-IC silicon-based packaging technologies have advanced the state of the art beyond SoC technologies which first united digital, analog, and memory functions on a single chip in the '90s. These ... » read more

Research Bits: Nov. 21


Graphene heater for phase-change switches Researchers from the University of Washington, Stanford University, Charles Stark Draper Laboratory, University of Maryland, and Massachusetts Institute of Technology designed an energy-efficient, silicon-based non-volatile switch that manipulates light through the use of a phase-change material and graphene heater. Aiming to reduce the power consum... » read more

Challenges And Solutions In Chip Design


Ansys is hosting IDEAS Digital Forum 2022, a no-cost virtual event that brings together industry executives and technical design experts to discuss the latest in EDA for Semiconductors, Electronics, and Photonics. The December 6th on-line event starts with Keynote addresses from Raja Koduri from Intel, Pankaj Kukkal from Qualcomm, and insights into the metaverse from DP Prakash with start-up... » read more

On-Chip Power Distribution Modeling Becomes Essential Below 7nm


Modeling power distribution in SoCs is becoming increasingly important at each new node and in 3D-ICs, where tolerances involving power are much tighter and any mistake can cause functional failures. At mature nodes, where there is more metal, power problems continue to be rare. But at advanced nodes, where chips are running at higher frequencies and still consuming the same or greater power... » read more

Research Bits: Nov. 15


Low temperature 3D bonding Scientists from Osaka University developed a new method for the direct three-dimensional bonding of copper electrodes using silver layers. The method works at low temperatures and does not require external pressure. "Our process can be performed under gentle conditions, at relatively low temperatures and without added pressure, but the bonds were able to withstand... » read more

Managing IP In Heterogeneous Designs


Increasing complexity and heterogeneity is creating huge challenges for tracking different versions of IP over the lifetime of chips. Pedro Pires, applications engineer at ClioSoft, talks about the implications of IP reuse in a complex, multi-IP context, including how different standards and database formats can affect IP tracking and why an interoperability layer is essential to tracking IP an... » read more

Predictive Health Monitoring In Functional Safety


Functional safety first became a major issue for the semiconductor industry in 2011 with the introduction of the ISO 26262 standard for implementing functional safety in the automotive industry. Before that, functional safety had already been standardized in a general manner for all industries since the end of the 1990s in IEC 61508. However, in the field of industrial automation, where the IEC... » read more

Taking Power Much More Seriously


An increasing number of electronic systems are becoming limited by thermal issues, and the only way to solve them is by elevating energy consumption to a primary design concern rather than a last-minute optimization technique. The optimization of any system involves a complex balance of static and dynamic techniques. The goal is to achieve maximum functionality and performance in the smalles... » read more

Accelerating IoT Designs: Designing For Low Power In The Era Of Smart Everything


Most of us have become accustomed to interacting with the ubiquitous technology ecosystem daily (if not hourly). From fitness trackers, smart vacuums, and semi-autonomous vehicles to the smart home devices that wake us up every morning, there’s no denying that the internet of things (IoT) boom has proliferated in every aspect of our lives. At the core of this instant, at-our-fingertips conn... » read more

Are You Paying Proper Attention To Your ESD Design Windows?


Electrostatic discharge (ESD) issues in integrated circuit (IC) chip designs have become more critical at advanced semiconductor process nodes, due to shrinking transistor dimensions and oxide layer thickness [1]. There are many ESD design rules and flows that designers check for common ESD issues, such as topological checks for the existence of ESD protection devices, current density (CD) chec... » read more

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