category: Manufacturing, Packaging and Materials

category: IoT, Security & Automotive

Five Questions To Ask When Selecting A Temporary Bonding And Debonding System
By Jessica Albright - 15 Aug, 2024 - Comments: 0

High-bandwidth memory blocks (HBM), microprocessors, field-programmable gate arrays (FPGA), AI accelerators, and other devices used in advanced system-level packaging all rely on temporary bonding and debonding systems to shrink their footprint. Understanding which properties play the most crucial role in device reliability and efficient production will ensure you are maximizing your yield, whi... » read more

Why Small Fab And Assembly Houses Are Thriving
By Bryon Moyer - 15 Aug, 2024 - Comments: 0

High-volume products get more than their fair share of attention in the semiconductor world, but most chips don't fit into that category. While a few huge fabs and offshore assembly and test (OSAT) houses process enormous volumes of chips, small fabs and packaging lines serve for lower volumes, specialized technology, and prototyping. “There are companies that run literally one lot of 25 w... » read more

Securing Supply Chains At SEMICON West 2024
By John Cooney - 15 Aug, 2024 - Comments: 0

Jose Fernandez, U.S. Under Secretary of State for Economic Growth, Energy, and the Environment, sat down with Joe Stockunas, President of SEMI Americas, for a fireside chat on the CEO Summit keynote stage at SEMICON West 2024. In the Securing Critical Supply Chains for the 21st Century discussion, Fernandez emphasized the need to form partnerships to address vulnerabilities as the key to cre... » read more

Reasons To Know IGZO
By Katherine Derbyshire - 15 Aug, 2024 - Comments: 0

Interest in monolithic 3D integration is driven by both compute-in-memory applications and a more general need for increased circuit density. Compute-in-memory architectures seek to reduce the power requirements of machine learning workloads, which are dominated by the movement of data between memory and logic components. Even in conventional architectures, though, placing high-density, high-ba... » read more

Key Technologies To Extend EUV To 14 Angstroms
By Laura Peters - 29 Jul, 2024 - Comments: 3

The top three foundries plan to implement high-NA EUV lithography as early as 2025 for the 18 angstrom generation, but the replacement of single exposure high-NA (0.55) over double patterning with standard EUV (NA = 0.33) depends on whether it provides better results at a reasonable cost per wafer. So far, 2024 has been a banner year for high-numerical aperture EUV lithography. Intel Foundry... » read more

Legacy Process Nodes Going Strong
By Bryon Moyer - 23 Jul, 2024 - Comments: 0

While all eyes tend to focus on the leading-edge silicon nodes, many mature nodes continue to enjoy robust manufacturing demand. Successive nodes stopped reducing die cost at around the 20nm node. “In the finFET era of processes, esoteric process requirements necessary to move technology forward with each generation have added significant cost and complexity,” explained Andrew Appleby, p... » read more

Precision Patterning Options Emerge For Advanced Packaging
By Gregory Haley - 23 Jul, 2024 - Comments: 0

The chip industry is ratcheting up investments in advanced packaging as it strives to keep pace with demands for increased functionality and higher performance, including novel patterning technologies that can reduce costs and speed time to market. Success in advanced packages is partly dependent on effectively managing the interconnectivity between the chips, which requires increasingly pre... » read more

Improving Line Edge Roughness Using Virtual Fabrication
By Qingpeng Wang - 23 Jul, 2024 - Comments: 0

Line edge roughness (LER) is a variation in the width of a lithographic pattern along one edge of a structure inside a chip. Line edge roughness can be a critical variation source and defect mechanism in advanced logic and memory devices and can lead to poor device performance or even device failure. [1~3]. Deposition-etch cycling is an effective technique to reduce line edge roughness. In this... » read more

Reliability Performance Of S-Connect Module (Bridge Technology) For Heterogeneous Integration Packaging
By Heejun Jang - 23 Jul, 2024 - Comments: 0

With the explosive increase in demand for artificial intelligence (AI), autonomous driving, Internet of Things (IoT), data centers, augmented reality and virtual reality (AR/VR), the market of high-performance computing (HPC) applications is growing rapidly [2]. And, the HPC market requires high processing speed, fast network clusters and large parallel computing. To meet the market requirement... » read more

Metrology Analysis Tool For Photolithography Process Characterization At Advanced Nodes
By Wolfgang Demmerle - 23 Jul, 2024 - Comments: 0

Continued scaling of integrated circuits to smaller dimensions is still a viable way to increase compute power, achieve higher memory cell density, or reduce power consumption. These days, chip makers are using single-digit nanometer figures or even Angstrom to label their manufacturing technology nodes, which are associated with the size of features patterned during the lithography process. ... » read more

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