Stop The Drip-Drip-Drip Of Intermittent In-Line Wafer Defects And Increase Your Yields


Full-blown process excursions that affect every wafer are comparatively easy for fabs to detect and fix. However, “onesie-twosie,” lower-volume excursions can go unresolved for months or even years. Some process engineers call them "slow moving excursions.” And over time, those low-volume defects can add up to significant yield losses. Ignoring a problem Some intermittent process excurs... » read more

New Standardized Semiconductor Cybersecurity Assessment (SSCA) Strengthens Security And Collaboration Across Global Supply Chain


The SEMI Semiconductor Manufacturing Cybersecurity Consortium (SMCC) Work Group 3 (Supply Chain Cybersecurity) just released a major work product that will have a significant and lasting positive impact on the industry: the “Standardized Semiconductor Cyber Assessment (SSCA)” questionnaire. Creating a common security assessment process for device makers, equipment suppliers, software s... » read more

Why In-Memory Computation Is So Important For Edge AI


In popular media, “AI” usually means large language models running in expensive, power-hungry data centers. For many applications, though, smaller models running on local hardware are a much better fit. Autonomous vehicles need to respond in real-time, without data transmission delays. Medical and industrial applications often depend on sensitive data that cannot be shared with third par... » read more

Using AI/ML To Find And Correlate IC Test Data


What causes low yield in wafers? Usually it's due to design or process changes, but sometimes yield issues occur even if there haven't been any changes from one manufacturing lot to the next. Finding the cause requires some sleuthing, and the best approach for pinpointing problems is to mine design, process, and manufacturing data, and to correlate that data by date and time, by which equipment... » read more

Smarter Packaging: How AI is Reshaping Assembly and Materials Control


When a multi-die package worth $500 fails final test because of a defect that originated three process steps earlier, the economics of advanced packaging become painfully clear. Each excursion carries downstream costs that ripple across assembly, final test, and even system qualification. As packaging margins tighten, the industry is betting on artificial intelligence (AI) to catch those pro... » read more

Voltage Regulation Moves Into The Package


Integrated circuits require a variety of voltages and a wide range of currents, typically supplied by voltage regulators. But increasing power density is resulting in higher power delivery losses. Moving those regulators closer to the chips they power can reduce those losses. Co-packaging them holds the most promise, but it comes with challenges. “What people have been talking about, ev... » read more

Mitigating Warpage In Multi-Chiplet Systems


Warpage of dies, redistribution layers, and interposers is a growing problem in multi-chiplet packages, and it can have a dramatic impact on the behavior and reliability of these devices. Multiple factors contribute to warpage, including larger chip sizes, severe thinning of the silicon substrate, temporary bonding and debonding processes, and scaling of bump pitch and size. Each of these ca... » read more

Virtual Metrology In Semiconductor Manufacturing


Fourth in a seven-part series: Virtual metrology may never be 100% perfect because of the almost unlimited number of changes in a fab tools and the unique chip and wafer designs they're being used to process. But there are places where virtual metrology does make sense. Jon Herlocker, vice president and general manager of software analytics at Cohu, talks about why virtual metrology will never ... » read more

Enhancing Clip Attach Vision Accuracy In Semiconductor Manufacturing


In the semiconductor industry, the outsourced semiconductor assembly and test (OSAT) sector plays a pivotal role in the global technology landscape. As the backbone of electronic device manufacturing, OSAT companies are entrusted with the critical task of assembly, testing, and packaging of devices. Maintaining quality in OSAT operations is of paramount importance, as it directly impacts the pe... » read more

Breaking The Copper Bottleneck With Molybdenum Hybrid Metallization


Scaling the back end of line (BEOL) in advanced semiconductor logic devices is a major challenge. Metal lines and via filling in BEOL have historically used copper (Cu) as the electrical conductor. But as device dimensions shrink, Cu use has become problematic. The small critical dimensions (CD) of the Cu metal lines and vias in the latest BEOL structures have created an increase in resistance,... » read more

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