category: Editor’s Note

category: IoT, Security & Automotive

Uncertainty Ahead
By Ed Sperling - 11 Apr, 2013 - Comments: 0

If finFETs work as planned, it’s likely they will show up in every complex SoC for decades to come. Adding another dimension to transistors has enormous potential at advanced nodes, and maybe even at older nodes. 3D transistors also could be part of stacked die, and they can be combined with fully depleted SOI—two other options for reducing power. Moreover, it’s likely that whatever G... » read more

Throw In The Kitchen Sink
By Ed Sperling - 05 Apr, 2013 - Comments: 0

By Ed Sperling The number of options available for reducing power and improving performance are increasing for the first time in a decade. This is good news for chipmakers. It’s far less clear who stands to benefit on the tools, IP, capital equipment and manufacturing side. Choice is always a good thing in design. It allows teams to trade off one IP block for another, based upon the needs... » read more

Let The IP Wars Begin
By Ed Sperling - 14 Mar, 2013 - Comments: 0

y Ed Sperling Nature abhors a vacuum. Customers abhor a monopoly. It appears both problems are now being solved in the EDA world—assuming approval by regulatory agencies, of course. There have been two concerns facing chipmakers in regards to third-party IP. One is political. Most large companies spent millions of dollars and thousands of frustrating man-hours developing their own interna... » read more

LP Verification
By Ed Sperling - 08 Mar, 2013 - Comments: 0

Functional verification has been a consideration throughout the design flow for the past several process nodes. Low power verification has been more of an afterthought. That’s beginning to change, though, as the challenge of integrating IP blocks and the physical effects of shrinking wires and RC delays in interconnects begin affecting power and performance in designs. What’s becoming cl... » read more

Unified Power Intent
By Ed Sperling - 01 Mar, 2013 - Comments: 0

The next version of the Unified Power Format has been approved, bridging the major differences between UPF/IEEE 1801 and the Common Power Format. For anyone who works in low-power verification, this is very good news. The new standard is the result of an unprecedented collaboration by chipmakers and EDA companies, and the people who devised a solution to this problem deserve a big pat on the... » read more

Bit Mapping
By Ed Sperling - 22 Feb, 2013 - Comments: 0

The rule of thumb for semiconductor manufacturing is that big breakthroughs tend to last a decade, or about five process nodes. While the transistor already has spanned more than five decades and the IC more than four decades, the technology used to create them typically only lasts about one. 193nm lithography has been around more than a decade. Bets were being made publicly back at 45nm—o... » read more

Proving IP
By Ed Sperling - 14 Feb, 2013 - Comments: 0

As the amount of commercially available IP in a design increases, so does the level of confusion. Unlike those giant yellow stickers you get with a major appliance that tell you how much energy you’re likely to use over the course of a year and the projected cost range, there’s no such information available for semiconductor IP. In fact, there’s even resistance to provide that kind of ... » read more

Math Questions
By Ed Sperling - 08 Feb, 2013 - Comments: 0

The race is on. GlobalFoundries, TSMC, Samsung, IBM and Intel are all neck deep in research, test chips, variability, lithography and three-dimensional transistor designs. For the first time, though, the goal very publicly has shifted from performance and area to energy efficiency. Being able to double battery life with existing performance over the next couple nodes could mean smart phones ... » read more

Moore’s Law Revisited
By Ed Sperling - 17 Jan, 2013 - Comments: 0

Moore’s Law, for all its re-interpretation, remains an iconic economic statement about doubling transistors over a fixed period of time—despite the fact that the time frame has changed at least twice since Gordon Moore first postulated his formula for shrinking features. Still, you don’t shrink feature sizes unless there is some economic benefit, and increasingly you don’t get an econom... » read more

Brother, Can You Spare An Electron?
By Ed Sperling - 11 Jan, 2013 - Comments: 0

Every now and then in semiconductor design we come to a crossroads where we have to start thinking about problems differently. At 10nm we will be forced to do that again. The problem—or opportunity, depending on your vantage point—this time involves electrons. While they’ve become increasingly difficult to manage in ever-thinner wires, where RC delay is producing unwanted heat, and in ... » read more

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