Throw In The Kitchen Sink

The number of options available to chip designers is increasing. Which ones will they choose?


By Ed Sperling
The number of options available for reducing power and improving performance are increasing for the first time in a decade. This is good news for chipmakers. It’s far less clear who stands to benefit on the tools, IP, capital equipment and manufacturing side.

Choice is always a good thing in design. It allows teams to trade off one IP block for another, based upon the needs of a particular application or even a single design, and to weigh one approach versus another in everything from layout to memory configuration. Will it be sold in huge volume or into markets where price isn’t an issue—think data centers, for example—or will it be used in a highly competitive consumer device?

Even Moore’s Law seems to be bending slightly to accommodate all of this. The work on directed self-assembly is making huge strides, which could make it a reality at 10nm or 7nm if extreme ultraviolet lithography never becomes viable. There are other options, too, such as multi-beam, which could be an alternative to multipatterning using 193nm immersion lithography.

But that’s only one part of the options menu. GlobalFoundries just had a big breakthrough in 3D stacking, rolling out a middle-via approach to TSVs that appears to make it commercially viable. Through-silicon vias have been problematic from a manufacturing standpoint because it’s like putting a giant pipe into the substrate. Having a process that is repeatable goes a long way toward offering performance improvements in designs, because the distance between two chips is often less than across a single die, and it requires less power because the pipe is larger and the distance is shorter. Moreover, there are fewer RC issues that come with thinner wires, less electromigration to deal with, and less routing congesting because memory can be approached from another dimension.

A third option is fully depleted SOI at 28nm, which avoids the need for designing finFETs. While finFETs offer major improvements in controlling leakage, similar gains can be made with FD-SOI. STMicroelectronics has made the most of that node, and many companies are expected to follow suit. By adding body biasing, ST has demonstrated similar gains to designing with finFETs.

IBM is working on all of the above. The company likely will offer finFETs on FD-SOI, possibly developed with directed self-assembly, and ultimately in stacked configurations. Others will mix and match options, depending upon the application, cost considerations, and whether it’s a platform for derivatives.

But this raises some interesting questions on the tooling and equipment side. If all of these options are available, and the complexity of each of them is rising—and subsequently the cost—then what will customers use in volume to warrant the huge investment in tools? If they opt out at 28nm using FD-SOI, then older process technology and tools work just fine. If they move to finFETs, they need more advanced EDA tools and the foundries have to invest in new equipment. And if they use stacked configurations, that poses a new set of challenges that require more advanced tools, more complicated testing and new packaging equipment.

While options are great for designers, they come with a huge price tag and many more risks for the companies that make those designs possible. End markets are fragmenting, but so are the design choices that need to be made to serve those markets.

—Ed Sperling

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