category: Test, Measurement and Analytics

category: IoT, Security & Automotive

Unlocking The Value Of Yield
By Marc Hutner - 11 Mar, 2025 - Comments: 0

Have you stopped to consider the impact of yield on your overall product cost? Of course you did, when you considered your yield targets and set your product goals. But is it good enough to stop once the goals are achieved, or should you find ways to drive additional value into your organization once production has begun? What is the value of a 1% improvement in product yield? The short answer ... » read more

Cutting IC Manufacturing Costs By Combining Data
By Anne Meixner - 11 Mar, 2025 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss the benefits of incorporating financial data into fab floor decision-making, including what kind of cost data is most useful, with Dieter Rathei, CEO of DR Yield; Jon Holt, senior director of product management at PDF Solutions, Alex Burlak, vice president of advanced analytics and test at proteanTecs; and Dirk de Vries, techni... » read more

Reversible Chain Diagnosis
By Siemens EDA - 11 Mar, 2025 - Comments: 0

For advanced technologies, the industry is seeing very complicated silicon defect types and defect distribution. One consequence is that scan chain diagnosis becomes more difficult. To improve the resolution of scan chain diagnosis, Tessent Diagnosis can use new scan chain test patterns to leverage a reversible scan chain architecture. This paper describes the novel scan chain architecture t... » read more

Silicon Photonics Raises New Test Challenges
By Jeorge Hurtarte - 11 Mar, 2025 - Comments: 0

Semiconductor devices continuously experience advancements leading to technology and innovation leaps, such as we see today for applications in AI high-performance computing for data centers, edge AI devices, electric vehicles, autonomous driving, mobile phones, and others. Recent technology innovations include Angstrom-scale semiconductor processing nodes, high-bandwidth memory, advanced 2.5D/... » read more

AI Semiconductors Require An Integrated Test Solution
By Ira Leventhal - 11 Mar, 2025 - Comments: 0

The rapid proliferation of generative pre-trained transformers based on large language models (LLMs) is driving growth in the market for chips that can run the LLMs and other artificial intelligence (AI) and machine learning (ML) applications. Several types of chips hold promise for accelerating AI computing. Graphical processing units (GPUs) have proven to be capable solutions for the server/c... » read more

Failure To Launch
By Gregory Haley - 11 Mar, 2025 - Comments: 1

Failure analysis (FA) is an essential step for achieving sufficient yield in semiconductor manufacturing, but it’s struggling to keep pace with smaller dimensions, advanced packaging, and new power delivery architectures. All of these developments make defects harder to find and more expensive to fix, which impacts the reliability of chips and systems. Traditional failure analysis techniqu... » read more

Full-Chip Voltage Contrast Inference Using Deep Learning; You Only Look Once: Voltage Contrast (YOLO-VC)
By PDF Solutions - 11 Mar, 2025 - Comments: 0

Abstract: The electron beam inspection methodology for voltage contrast (VC) defects has been widely adopted in the early stages of sub-10nm logic and memory technology development, as well as in new product introductions. However, due to throughput limitations, full-chip inspection at the 300mm wafer scale remains impractical for yield ramp and production applications. To address this challeng... » read more

Material Properties of Si/SiGe Multi-layer Stacks For CFETs (Imec, Ghent U, et al.)
By Technical Paper Link - 19 Feb, 2025 - Comments: 0

A new technical paper titled "Epitaxial Si/SiGe Multi-Stacks: From Stacked Nano-Sheet to Fork-Sheet and CFET Devices" was published by researchers at Imec and Ghent University, et al. Abstract "After a short description of the evolution of metal-oxide-semiconductor device architectures and the corresponding requirements on epitaxial growth processes, the manuscript describes the material pr... » read more

Optimizing DFT With AI And BiST
By Gregory Haley - 12 Feb, 2025 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to explore how AI impacts design for testability, with Jeorge Hurtarte, senior director of product marketing in the Semiconductor Test Group at Teradyne; Sri Ganta, director of test products at Synopsys; Dave Armstrong, principal test strategist at Advantest; and Lee Harrison, director of Tessent automotive IC solutions at Siemens EDA. Wh... » read more

Innovations Driving The Advanced Packaging Roadmap: Part Two
By Keith Best - 11 Feb, 2025 - Comments: 0

As the advanced packaging world enters the AI era, manufacturers are exploring ways to extend the life cycle of organic substrates and successfully introduce glass substrates to high volume manufacturing. In last month’s blog, “Innovations Driving The Advanced Packaging Roadmap: Part One,” we discussed the challenges of organic and glass substrates as the industry marches toward sub-2µm ... » read more

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