category: Test, Measurement and Analytics

category: IoT, Security & Automotive

Rethinking Chip Reliability For Harsh Conditions
By Gregory Haley - 10 Jun, 2025 - Comments: 0

As semiconductors push into environments once considered untenable, reliability expectations are being redefined. From the vacuum of space and the inside of jet engines to deep industrial automation and electrified drivetrains, chips now must endure extreme temperature swings, corrosive atmospheres, mechanical vibration, radiation, and unpredictable power cycles, all while delivering increasing... » read more

High-Quality Data Needed To Better Utilize Fab Data Streams
By Anne Meixner - 10 Jun, 2025 - Comments: 0

Fab operations have wrestled with big data management issues for decades. Standards help, but only if sufficient attention to detail is taken during collection. Semiconductor wafer manufaFcturing represents one of the most complex manufacturing processes in the world. With each generation of process improvement comes more sophisticated fab equipment, new process recipes, and exponential incr... » read more

The Data Dilemma In Semiconductor Testing And Why It Matters: Part 1
By Roberto Colecchia - 10 Jun, 2025 - Comments: 0

In today’s semiconductor industry, machine learning (ML) is no longer a buzzword — it’s an operational necessity. From optimizing test flows to identifying device drifts and executing advanced analytics like VMIN or trimming, ML-based applications are increasingly used to boost yields, improve quality, and lower test costs. But there’s a catch. To make these intelligent applications ... » read more

Stress-Related Local Layout Effects In FinFET Technology And Device Design Sensitivity
By PDF Solutions - 10 Jun, 2025 - Comments: 0

Abstract: "Transistor characteristics in advanced technology nodes are strongly impacted by devices design and process integration choices. Variation in the layout and pattern configuration in close proximity to the device often causes undesirable sensitivities known as Local Layout Effects (LLEs). One of the sensitivities is related to carrier mobility dependence on mechanical stress, modul... » read more

Problems In Testing AI Chips
By Ed Sperling - 20 May, 2025 - Comments: 0

As AI chips get larger, it becomes much harder to test them. Today, there can be as many as 22,000 pins on a 150mm² die, but in the future that number may increase to 80,000 pins. That creates a huge challenge for the fabs and the testers. Jack Lewis, chief technologist at Modus Test, talks about the intricacies of testing these complex devices, from maintaining contact with those pins even on... » read more

Overlay, Critical Dimension, And Z-Height Metrology Solutions For Advanced Packaging
By Al Gamble - 08 May, 2025 - Comments: 0

The consumer’s thirst for AI-based applications is powering the ever-evolving electronics industry. Applications delivering higher levels of information in human language-like form, smarter at-home gadgets, the ability to receive a medical diagnosis without a doctor’s visit and the convenience of autonomous vehicles are among the applications powering this thirst. To better enable these app... » read more

AI For Test: The New Frontier
By Christophe Begue - 08 May, 2025 - Comments: 0

Dr. Ming Zhang, PDF Solutions vice president of Fabless Solutions, delivered the keynote at the TestConX 2025 conference in March. As he began his presentation, Ming borrowed the “learn, explore and share” line from Ira Feldman, the organizer of the conference, to set the tone of his talk. He promised to share what he and PDF Solutions learned and what’s useful and what’s not useful as ... » read more

Better ATPG To Minimize Chip Test Time And Cost
By Hari Mani - 08 May, 2025 - Comments: 0

As chips get ever bigger and more complex, the electronic design automation (EDA) industry must innovate constantly to keep up. Engineers expect every new generation of silicon to be modeled, simulated, laid out, and checked in about the same time with the same effort, despite the growth in die size and density. One area of particular focus is manufacturing test. Any effort expended to reduce t... » read more

Shifting Left With DFT To Optimize Productivity, Testability, And Time-To-Market
By Siemens EDA - 08 May, 2025 - Comments: 0

This paper discusses one of the Siemens EDA shift-left strategies in the RTL-to-signoff flow: shift-left design-for-test (DFT). Tessent RTL Pro software automates the analysis and insertion of Tessent VersaPoint test point technology, LBIST-OST test points, dedicated scan wrapper cells and x-bounding logic as behavioral code at the RTL level. Tessent RTL Pro builds on Tessent’s market-leading... » read more

Identifying Sources Of Silent Data Corruption
By Laura Peters - 08 May, 2025 - Comments: 0

Silent data errors are raising concerns in large data centers, where they can propagate through systems and wreak havoc on long-duration programs like AI training runs. SDEs, also called silent data corruption, are technically rare. But with many thousands of servers, which contain millions of processors running at high utilization rates, these damaging events become common in large fleets. ... » read more

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