System-Level Verification Tackles New Role

By Brian Bailey - 28 Apr, 2016 - Comments: 0

Wally Rhines, chairman and CEO of Mentor Graphics, gave the keynote at DVCon this year. He said that if you pull together a bunch of pre-verified IP blocks, it does not change the verification problem at the system level. That sounds like a problem. There are assumptions made that the IP blocks work to a reasonable degree, and that when performing system-level verification the focus is not a... » read more

2.5D Becomes A Reality

By Ed Sperling - 27 Apr, 2016 - Comments: 0

Semiconductor Engineering sat down to discuss 2.5D and advanced packaging with Max Min, senior technical manager at [getentity id="22865" e_name="Samsung"]; Rob Aitken, an [getentity id="22186" comment="ARM"] fellow; John Shin, vice president at [getentity id="22903" e_name="Marvell"]; Bill Isaacson, director of ASIC marketing at [getentity id="22242" e_name="eSilicon"]; Frank Ferro, senior di... » read more

Are Simulation’s Days Numbered?

By Brian Bailey - 26 Apr, 2016 - Comments: 0

Semiconductor Engineering sat down to discuss the limitations of simulation in more complex designs with [getperson id="11049" comment="Michael McNamara"], CEO of [getentity id="22716" comment="Adapt-IP”]; Pete Hardee, product management director at [getentity id="22032" e_name="Cadence"]; David Kelf, vice president of marketing for for [getentity id="22395" e_name="OneSpin Solutions"]; Lauro... » read more

2.5D Becomes A Reality

By Ed Sperling - 14 Apr, 2016 - Comments: 2

Where Is Next-Gen Lithography?

By Mark LaPedus - 11 Apr, 2016 - Comments: 1

Semiconductor Engineering sat down to discuss lithography and photomask technologies with Greg McIntyre, director of the Advanced Patterning Department at Imec; Harry Levinson, senior fellow and senior director of technology research at GlobalFoundries; Uday Mitra, vice president and head of strategy and marketing for the Etch Business Unit and Patterning Module at Applied Materials; Naoya Haya... » read more

Are Simulation’s Days Numbered?

By Brian Bailey - 06 Apr, 2016 - Comments: 3

Semiconductor Engineering sat down to discuss the limitations of simulation in more complex designs with [getperson id="11049" comment="Michael McNamara"], CEO of [getentity id="22716" comment="Adapt-IP”]; Pete Hardee, product management director at [getentity id="22032" e_name="Cadence"]; David Kelf, vice president of marketing for [getentity id="22395" e_name="OneSpin Solutions"]; Lauro Riz... » read more

Where Is Next-Gen Lithography?

By Mark LaPedus - 31 Mar, 2016 - Comments: 2

Semiconductor Engineering sat down to discuss lithography and photomask technologies with Greg McIntyre, director of the Advanced Patterning Department at [getentity id="22217" comment="Imec"]; Harry Levinson, senior fellow and senior director of technology research at [getentity id="22819" comment="GlobalFoundries"]; Uday Mitra, vice president and head of strategy and marketing for the Etch Bu... » read more

Are Simulation’s Days Numbered?

By Brian Bailey - 24 Mar, 2016 - Comments: 0

In the latest EDAC report, the value of IP surpassed the value of CAE tools for the first time. Verification tools are an important part of establishing confidence in IP blocks and simulation has been the mainstay of that IP verification strategy. But simulation is under increasing pressure, particularly for full-chip and SoC verification, because it has failed to scale. While it still remains ... » read more

Where Is Next-Gen Lithography?

By Mark LaPedus - 17 Mar, 2016 - Comments: 4

Upcoming Hurdles For The Semiconductor Industry

By Ann Mutschler - 01 Feb, 2016 - Comments: 0

Semiconductor Engineering sat down to discuss upcoming challenges and hurdles to overcome for the semiconductor industry with Vic Kulkarni, senior vice president and general manager, RTL Power Business at Ansys-Apache; Chris Rowen, Fellow and CTO, IP Group at Cadence; Subramani Kengeri, vice president, Global Design Solutions at GLOBALFOUNDRIES; Simon Davidmann, CEO of Imperas Software; Michael... » read more

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Knowledge Centers
Entities, people and technologies explored

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3.5D: The Great Compromise

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by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

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Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

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Megafabs churning out the most advanced processors are not the only game in town.

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category: Round Tables

category: IoT, Security & Automotive

System-Level Verification Tackles New Role

2.5D Becomes A Reality

Are Simulation’s Days Numbered?

2.5D Becomes A Reality

Where Is Next-Gen Lithography?

Are Simulation’s Days Numbered?

Where Is Next-Gen Lithography?

Are Simulation’s Days Numbered?

Where Is Next-Gen Lithography?

Upcoming Hurdles For The Semiconductor Industry