5/3nm Wars Begin


Several foundries are ramping up their new 5nm processes in the market, but now customers must decide whether to design their next chips around the current transistor type or move to a different one at 3nm and beyond. The decision involves the move to extend today’s finFETs to 3nm, or to implement a new technology called gate-all-around FETs (GAA FETs) at 3nm or 2nm. An evolutionary step f... » read more

Automakers Changing Tactics On Reliability


Automakers are beginning to rethink how to ensure automotive electronics will remain reliable over their projected lifetimes, focusing their efforts on redundancy, more data-centric architectures and continued testing throughout the life of a vehicle. It is still too early to really know how automotive chips actually will perform over the next 15 to 20 years, especially AI logic developed at... » read more

Defining And Improving AI Performance


Many companies are developing AI chips, both for training and for inference. Although getting the required functionality is important, many solutions will be judged by their performance characteristics. Performance can be measured in different ways, such as number of inferences per second or per watt. These figures are dependent on a lot of factors, not just the hardware architecture. The optim... » read more

5 Major Shifts In Automotive


Much of the automotive industry has begun repositioning and retrenching over the past few months, pushing back the projected rollout for fully autonomous vehicles and changing direction on power sources and technology used in the next-generation of electric vehicles. Taken together, these shifts mark a significant departure for traditional automakers, which find themselves playing catch-up t... » read more

Multi-Patterning EUV Vs. High-NA EUV


Foundries are finally in production with EUV lithography at 7nm, but chip customers must now decide whether to implement their next designs using EUV-based multiple patterning at 5nm/3nm or wait for a new single-patterning EUV system at 3nm and beyond. This scenario revolves around ASML’s current extreme ultraviolet (EUV) lithography tool (NXE:3400C) versus a completely new EUV system with... » read more

Power Complexity On The Rise


New chip architectures and custom applications are adding significant challenges to chip design and verification, and the problems are becoming much more complex as low power is added into the mix. Power always has been a consideration in design, but in the past it typically involved different power domains that were either on, off, or in some level of sleep mode. As hardware architectures s... » read more

Revving Up For Edge Computing


The edge is beginning to take shape as a way of limiting the amount of data that needs to be pushed up to the cloud for processing, setting the stage for a massive shift in compute architectures and a race among chipmakers for a stake in a new and highly lucrative market. So far, it's not clear which architectures will win, or how and where data will be partitioned between what needs to be p... » read more

Solving The Memory Bottleneck


Chipmakers are scrambling to solve the bottleneck between processor and memory, and they are turning out new designs based on different architectures at a rate no one would have anticipated even several months ago. At issue is how to boost performance in systems, particularly those at the edge, where huge amounts of data need to be processed locally or regionally. The traditional approach ha... » read more

New Security Risks Create Need For Stealthy Chips


Semiconductors are becoming more vulnerable to attacks at each new process node due to thinner materials used to make these devices, as well as advances in equipment used to simulate how those chips behave. Thinner chips are now emitting light, electromagnetic radiation and various other types of noise, which can be observed using infrared and acoustic sensors. In addition, more powerful too... » read more

The Race To Next-Gen 2.5D/3D Packages


Several companies are racing each other to develop a new class of 2.5D and 3D packages based on various next-generation interconnect technologies. Intel, TSMC and others are exploring or developing future packages based on one emerging interconnect scheme, called copper-to-copper hybrid bonding. This technology provides a way to stack advanced dies using copper connections at the chip level,... » read more

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