Trouble Ahead For IC Verification

By Brian Bailey - 30 May, 2024 - Comments: 0

Verification complexity is roughly the square of design complexity, but until recently verification success rates have remained fairly consistent. That's beginning to change. There are troubling signs that verification is collapsing under the load. The first-time success rate fell (see figure 1) in the last survey conducted by Wilson Research, on behalf of Siemens EDA, in 2022. A new survey ... » read more

A Unified Solution for End-to-End Low Power Verification

By Synopsys - 29 May, 2024 - Comments: 0

Low power designs are becoming increasingly prevalent in modern electronic systems, driven by the need for energy-efficient devices. Ensuring the correctness of these designs is paramount, as even minor errors can lead to catastrophic consequences. To achieve verification closure for low power designs, a combination of static verification, dynamic simulation-based verification, formal verificat... » read more

Will Chiplet Adoption Mimic IP Adoption?

By Alphawave Semi - 29 May, 2024 - Comments: 0

If we look at the semiconductor industry expansion during the last 25 years, adoption of design IP in every application appears to be one of the major factors of success, with silicon technology incredible development by a x100 factor, from 250nm in 2018 to 3nm (if not 2nm) in 2023. We foresee the move to chiplet-based architecture to soon play the same role that SoC chip-based architecture and... » read more

Distribution of Currents In Via Arrays

By Siemens EDA - 29 May, 2024 - Comments: 0

It has become increasingly difficult in recent years to provide adequate PDNs on a PCB. The sheer number of different voltages, combined with increased current demands, makes distributing current around the board a substantial layout challenge. This paper demonstrates that by using appropriate and accurate simulations, combined with the improved intuition that such simulations bring, it is a ch... » read more

Considerations to Successfully Integrate Chiplets in Designs

By Keysight - 29 May, 2024 - Comments: 0

Chiplet integration is a promising approach to creating heterogeneous and complex system-on-chips (SoCs) with significant performance, power, scalability, flexibility, and cost benefits. However, chiplet integration also poses substantial design, verification, testing, and packaging challenges, requiring new standards and design methodologies. Electronic design automation (EDA) software and sim... » read more

Steady and Unsteady Full-Engine Simulations

By Cadence - 29 May, 2024 - Comments: 0

Discover the power of fully coupled steady and unsteady full-engine simulations. Say goodbye to traditional component-by-component methods. This innovative approach seamlessly integrates all engine components into a single, cohesive simulation framework, offering unparalleled accuracy and efficiency for aero-engine simulations. Key Takeaways: Steady and Time-Accurate: Achieve superio... » read more

Integrated, Turnkey Droop Response System: Heterogeneous IP Use Case

By Movellus - 29 May, 2024 - Comments: 0

Whether you serve the ADAS, PC, or networking market, chances are that your SoC is heterogeneous; containing general processors and application-specific accelerators. Your solution might have a systolic array for convolutions, a cluster of CPUs for application code, or a look-aside crypto engine for packet security. While application-specific accelerators significantly improve performance and p... » read more

Electromigration And IR Drop At Advanced Nodes

By Ed Sperling - 22 May, 2024 - Comments: 0

Manufacturing chips at 3nm and below is a challenge, but it's only part of the problem. Designing chips that can be manufactured and will actually work is potentially an even bigger problem. There is more data to sift through for place-and-route, less margin to pad a design, and there are more physical effects to contend with as transistors get taller, density increases, and chips age. Jeff Wil... » read more

Blog Review: May 22

By Jesse Allen - 22 May, 2024 - Comments: 0

Cadence's Sree Parvathy introduces Verilog-A, a high-level language that uses modules to describe the structure and behavior of analog systems and enables the top-down system to be defined before the actual transistor circuits are assembled. Siemens' Keith Felton suggests the process of package substrate design is improved by leveraging the collective expertise of multiple design domain spec... » read more

Blog Review: May 15

By Jesse Allen - 15 May, 2024 - Comments: 0

Cadence's Anika Sunda suggests that RISC-V has opened numerous doors for innovation and believes EDA tools can help bridge the knowledge gap and foster a growing community of RISC-V developers. Synopsys' Alessandra Costa chats with industry experts about challenges facing analog design, what's needed for multi-die designs, and the potential of AI. Siemens' Bill Ji explains why understandi... » read more

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