category: System-Level Design

category: IoT, Security & Automotive

Blog Review: May 21
By Jesse Allen - 21 May, 2025 - Comments: 0

Synopsys’ Frank Malloy listens in on a panel discussing the engineering challenges introduced by multi-die designs, from multi-physics interactions that impact power and thermal integrity to the availability of multi-die packages and industry standards. Siemens’ Bruce Caryl shows how to determine how much a design’s power delivery network is contributing to jitter on the output drivers... » read more

More Data, More Redundant Interconnects
By Ed Sperling - 19 May, 2025 - Comments: 0

The proliferation of AI dramatically increases the amount of data that needs to be processed, stored, and moved, accelerating the aging of signal paths through which that data travels and forcing chipmakers to build more redundancy into the interconnects. In the past, nearly all redundant data paths were contained within a planar chip using a relatively thick silicon substrate. But as chipma... » read more

Speeding Up Die-To-Die Interconnectivity
By Ed Sperling - 14 May, 2025 - Comments: 0

Disaggregating SoCs, coupled with the need to process more data faster, is forcing engineering teams to rethink the electronic plumbing in a system. Wires don't shrink, and just cramming more wires or thicker wires into a package are not viable solutions. Kevin Donnelly, vice president of strategic marketing at Eliyan, talks about how to speed up data movement between chiplets with bi-direction... » read more

Blog Review: May 14
By Jesse Allen - 14 May, 2025 - Comments: 0

Siemens’ Stephen V. Chavez finds that proper PCB high voltage spacing between conductive elements is key to reliability and understanding the principles of clearance (through-air spacing) and creepage (along-surface spacing) is critical. Cadence’s Frank Ferro checks out how the new HBM4 standard boosts bandwidth and addresses key issues in the data center, including the growing size of L... » read more

Blog Review: May 7
By Jesse Allen - 07 May, 2025 - Comments: 0

Cadence’s Mayank Bhatnagar examines the challenge of ensuring the functional safety of disaggregated designs and how UCIe can serve as a certified way to connect individual components. Siemens’ Charlie Olson explores the causes of inter-domain leakage when a DC path is formed between two power rails and how to overcome the limitations of traditional electrical rule checking. Synopsys�... » read more

From Tool Agents To Flow Agents
By Brian Bailey - 30 Apr, 2025 - Comments: 0

Experts At The Table: AI is starting to impact several parts of the EDA design and verification flows, but so far these improvements are isolated to single tool or small flows provided by a single company. What is required is a digital twin of the development process itself on which AI can operate. Semiconductor Engineering sat down with a panel of experts to discuss these issues and others, in... » read more

Blog Review: Apr. 30
By Jesse Allen - 30 Apr, 2025 - Comments: 0

Cadence’s Sree Parvathy points out how electrothermal analysis can help designers understand how temperature changes affect device behavior, such as mobility, threshold voltage, and saturation to mitigate potential failures due to thermal overstress. In a podcast, Siemens’ Conor Peick, Dale Tutt, and Mike Ellow chat about the transition towards software-defined products and why companies... » read more

How To Optimize Silicon Utilization To Improve PPA
By Ashish Darbari - 29 Apr, 2025 - Comments: 0

In the semiconductor industry, optimizing Power, Performance, and Area (PPA) is a key challenge for designers and architects. Balancing these three factors often involves making trade-offs. Improving one variable might lead to sacrificing others. For example, boosting performance may result in increased power consumption and a larger silicon area, or some power-reducing techniques might reduce ... » read more

Data Movement Is the Energy Bottleneck of Today’s SoCs
By Andy Nightingale - 24 Apr, 2025 - Comments: 0

In today’s AI-focused semiconductor landscape, raw compute performance alone no longer defines the effectiveness of a system-on-chip (SoC). The efficiency of data movement across the chip has become just as important. Whether designed for data centers or edge AI devices, SoCs must now prioritize data transport as a core architectural consideration. Moving data efficiently across the silicon f... » read more

Tape-Out Failures Are The Tip Of The Iceberg
By Brian Bailey - 24 Apr, 2025 - Comments: 5

The headline numbers for the new Wilson Research/Siemens functional verification survey are out, and it shows a dramatic decline in the number of designs that are functionally correct and manufacturable. In the past year, that has dropped from 24% to just 14%. Along with that, there is a dramatic increase in the number of designs that are behind schedule, increasing from 67% to 75%. Over the ne... » read more

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