Blog Review: Nov. 8


Siemens' Todd Westerhoff takes a look at the three stages of power integrity analysis for PCBs, challenges to board-level signal integrity, and best practices for getting the most accurate estimate of design performance. Synopsys' William Ruby provides a brief overview of the evolution of low-power design techniques and finds opportunities to reduce power and to make chip designs more energy... » read more

Coding And Debugging RISC-V


As monolithic device scaling continues to wind down and evolve toward increasingly heterogeneous designs, it has created an inflection point for chip architects to create customized cores that are much more energy efficient and faster than off-the-shelf processors. Zdeněk Přikryl, CTO of Codasip, talks about where RISC-V fits into this picture, using a modular ISA and custom instruction layer... » read more

Blog Review: November 1


Cadence’s Rich Chang finds that although UVM has being used for testbench creation for more than a decade, it is still challenging to debug problems that are inside of UVM testbench. Siemens’ Keith Felton suggests that early analysis in complex advanced packaging flows can enable designers to spot potential issues early to avoid built-in constructs that cause design failures and require ... » read more

What Will That Chip Cost?


In the past, analysts, consultants, and many other experts attempted to estimate the cost of a new chip implemented in the latest process technology. They concluded that by the 3nm node, only a few companies would be able to afford them — and by the time they got into the angstrom range, probably nobody would. Much has changed over the past few process nodes. Increasing numbers of startups... » read more

Unlocking The Power Of Edge Computing With Large Language Models


In recent years, Large Language Models (LLMs) have revolutionized the field of artificial intelligence, transforming how we interact with devices and the possibilities of what machines can achieve. These models have demonstrated remarkable natural language understanding and generation abilities, making them indispensable for various applications. However, LLMs are incredibly resource-intensi... » read more

The Limits Of AI-Generated Models


In several recent stories, the subject of models has come up, and one recurrent theme is that AI may be able to help us generate models of a required abstraction. While this may be true in some cases, it is very dangerous in others. If we generalize, AI should be good for any model where the results are predominantly continuous, but discontinuities create problems. Unless those are found and... » read more

Ensuring The Health And Reliability Of Multi-Die Systems


From generative AI tools that rapidly produce chatbot responses to high-performance computing (HPC) applications enabling financial forecasting and weather modeling, it’s clear we’re in a whole new realm of processing power demand. Given these compute-intensive workloads, monolithic SoCs are no longer capable to meet today’s processing needs. Engineering ingenuity, however, has answered t... » read more

Anatomy Of A System Simulation


The semiconductor industry has greatly simplified analysis by consolidating around a small number of models and abstractions, but that capability is breaking down both at the implementation level and at the system level. Today, the biggest pressure is coming from the systems industry, where the electronic content is a small fraction of what must be integrated together. Systems companies tend... » read more

System-on-Chip Integration Complexity And Hardware/Software Contracts


From the earliest days of my career, when designing chips, I have always navigated the interface between hardware and software for semiconductor design in my roles. My initial chip designs included video and audio encoding and decoding, supporting standards like MPEG and H.261. As acceleration parts of hardware/software systems, these had many Control and Status Registers (CSRs) to program. The... » read more

Rethinking Design, Workflow For 3D


In the 3D world, where NAND has hundreds of layers and packages come in intricate stacks, fresh graduates and veteran engineers alike are being confronted with design challenges that require a rethinking of both classic designs and traditional workflows, but without breaking the laws of physics. “There are pockets of things that have been on 3D for quite some time,” said Kenneth Larson, ... » read more

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