category: System-Level Design

category: IoT, Security & Automotive

Blog Review: October 4
By Jesse Allen - 04 Oct, 2023 - Comments: 0

Cadence's Felipe Goncalves checks out the Integrity and Data Encryption (IDE) feature in PCIe 6.0, a new layer inserted between the transection layer and data link layer with the goal of protecting against threats from physical attacks on the link. Siemens' Robin Bornoff, Daniel Berger, and Kai Liu explore the potential for large language models (LLMs) make the use of CAE tools simpler, more... » read more

Everyone’s A System Designer With Heterogeneous Integration
By Ann Mutschler - 02 Oct, 2023 - Comments: 0

The move away from monolithic SoCs to heterogeneous chips and chiplets in a package is accelerating, setting in motion a broad shift in methodologies, collaborations, and design goals that are felt by engineers at every step of the flow, from design through manufacturing. Nearly every engineer is now working or touching some technology, process, or methodology that is new. And they are inter... » read more

Application-Optimized Processors
By Ed Sperling - 29 Sep, 2023 - Comments: 0

Executing a neural network on top of an NPU requires an understanding of application requirements, such as latency and throughput, as well as the potential partitioning challenges. Sharad Chole, chief scientist and co-founder of Expedera, talks about fine-grained dependencies, why processing packets out of order can help optimize performance and power, and when to use voltage and frequency scal... » read more

Chip Industry Week In Review
By The SE Staff - 29 Sep, 2023 - Comments: 0

By Susan Rambo, Liz Allan, and Gregory Haley. TSMC rolled out the second version of its 3Dblox, which creates an infrastructure for stacking chiplets and other necessary components in a package, along with a standardized way of achieving that. Two novel features are chiplet mirroring for design reuse, and what is basically sandbox for power and thermal analysis of different design elements. ... » read more

The Federation Needs A Taxonomy
By Brian Bailey - 28 Sep, 2023 - Comments: 0

While putting together the story about federated simulation, it brought back memories of an earlier part of my career when I spent a lot of time looking at modeling abstractions and simulation frameworks. In the mid-1990s, the notions of re-using pre-designed blocks of IP started to become popular, but the fledgling industry was in disarray. Every IP block had a different set of deliverables... » read more

Accelerating Analog Design Migration
By Yuval Shay - 28 Sep, 2023 - Comments: 0

Today’s electronic chips are commonly comprised of a mix of analog, RF, and digital components, with increasing functionalities, complexities, and numbers of transistors reaching the trillions. While the digital side of the house can take advantage of automated design implementation tools, the analog world has always been more about doing things manually and in a very “custom” way—which... » read more

Network-on-Chips Enabling Artificial Intelligence/Machine Learning Everywhere
By Frank Schirrmeister - 28 Sep, 2023 - Comments: 0

Recently, I attended the AI HW Summit in Santa Clara and Autosens in Brussels. Artificial intelligence and machine learning (AI/ML) were critical themes for both events, albeit from different angles. While AI/ML as a buzzword is very popular these days in all its good and bad ways, in discussions with customers and prospects, it became clear that we need to be precise in defining what type of A... » read more

Formal Verification Best Practices: Investigating A Deadlock
By Laurent Arditi - 28 Sep, 2023 - Comments: 0

To ensure a design is deadlock free with formal verification, one approach consists in verifying that it is “always eventually” able to respond to a request. The wording is important. Regardless of the current state and the number of cycles we must wait, in the future the design must respond. This translates very nicely using a type of SystemVerilog Assertion called “liveness propertie... » read more

Industry Pressure Grows For Simulating Systems Of Systems
By Brian Bailey - 28 Sep, 2023 - Comments: 0

Most complex systems are designed in a top-down manner, but as the amount of electronic content in those systems increases, so does the pressure on the chip industry to provide high-level models and simulation capabilities. Those models either do not exist today, or they exist in isolation. No matter how capable a model or simulator, there never will be one that can do it all. In some cases,... » read more

AI Drives Need For Optical Interconnects In Data Centers
By Karen Heyman - 28 Sep, 2023 - Comments: 0

An explosion of data, driven by more sensors everywhere and the inclusion of AI/ML in just about everything, is ratcheting up the pressure on data centers to leverage optical interconnects to speed up data throughput and reduce latency. Optical communication has been in use for several decades, starting with long-haul communications, and evolving from there to connect external storage to ser... » read more

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